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Hold Time Violation during Gate level simulation

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jy0908

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Hi. All,

Could you guys help me understand this?

I have some hold time violations when I do gate level simulation of my design.

The problem is that
- No violatins when I use 100ns clock cycle time; always #50 clk = ~clk;
- Hold time violations when I use 10ns clcok cycle time; always #5 clk = ~clk;

My design is synthesized with 45nm lib, target frequency is 1GHz, and timescale is 1ns/1ps.

I don't know why hold time violations occur according to clock freqeuncy.
(As we know, hold time is independent of the frequency)

Could you give me any comment? Thanks in advance.
 

I think it is addressed in this forum 3 or 4 years back...


can you do a search in this forum.... i hope you get your answers if you do search
 

Hi,

as you I do not think that hold time is dependent on frequency

do you have a fully synchron design?
do you have clock domain crossings?
do you have multicycle or false pathes?
do you have clock divider?


can you see in the simulation wavetraces that the hold time depends on the frequency?

regards
 

Thank you :)

Unfortunately, It is a fully synchronous design, has only one clock domain, no muulti cycle and false pahts, and no clock drivers.
 

I think the problem may lies in the synthesis process. In other words, it has less to do with RTL code unless there is critical error. In Design Compiler, the clock you use for constraint and set fix hold may influence the final performance of circuit.
 

Why don't you debug it by yourself in the first place before asking the question to us who cannot even see the waveform ? if it's hold viols, the signal comes earlier than clock and you should be able to see the source of the problem on debussy/verdi, shouldn't you ?
We all learned the stuffs like that.
 

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