jy0908
Newbie level 5
Hi. All,
Could you guys help me understand this?
I have some hold time violations when I do gate level simulation of my design.
The problem is that
- No violatins when I use 100ns clock cycle time; always #50 clk = ~clk;
- Hold time violations when I use 10ns clcok cycle time; always #5 clk = ~clk;
My design is synthesized with 45nm lib, target frequency is 1GHz, and timescale is 1ns/1ps.
I don't know why hold time violations occur according to clock freqeuncy.
(As we know, hold time is independent of the frequency)
Could you give me any comment? Thanks in advance.
Could you guys help me understand this?
I have some hold time violations when I do gate level simulation of my design.
The problem is that
- No violatins when I use 100ns clock cycle time; always #50 clk = ~clk;
- Hold time violations when I use 10ns clcok cycle time; always #5 clk = ~clk;
My design is synthesized with 45nm lib, target frequency is 1GHz, and timescale is 1ns/1ps.
I don't know why hold time violations occur according to clock freqeuncy.
(As we know, hold time is independent of the frequency)
Could you give me any comment? Thanks in advance.