mrothe
Newbie level 3
Suppose I have an entity that has a generic that sets the width of one input. Now I want to have an output that has the minimum width to address each of the input bits.
A 12-bit example follows:
What I want to do is the following:
(Ok. I want to have "next greater integer of log2(width)", but that would make the pseudo code unnecessary unreadable.)
Is there VHDL syntax that can do this? What happens if the input is only two bits wide? I.e. the output needs to be std_logic instead of std_logic_vector.
If there is no such construct, what would be a good solution to accomplish this task? A second generic that describes the output of the entity and hope that the user instantiates the entity correctly?
A 12-bit example follows:
Code:
entity priority_encoder is
port (
input : in std_logic_vector(11 downto 0);
output : out std_logic_vector(3 downto 0)
);
end priority_encoder;
What I want to do is the following:
Code:
entity priority_encoder_ng is
generic (
width : positive;
);
port (
input : in std_logic_vector(width downto 0);
output : out std_logic_vector(log2(width) downto 0)
);
end priority_encoder_ng;
(Ok. I want to have "next greater integer of log2(width)", but that would make the pseudo code unnecessary unreadable.)
Is there VHDL syntax that can do this? What happens if the input is only two bits wide? I.e. the output needs to be std_logic instead of std_logic_vector.
If there is no such construct, what would be a good solution to accomplish this task? A second generic that describes the output of the entity and hope that the user instantiates the entity correctly?