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Clock Generation logic

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rocking1234

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Hi

Do anybody suggest a link or article to read about clock generation logic.

For example if I need to generate a Clock of 100Mhz with duty cycle 50%
 

you will always need a source clock, normally from a crystal. Then you can just pass it into a PLL to generate the correct frequency.

Logic generated clocks should generally be avoided in FPGAs.
 

rocking1234 said:
Hi

Do anybody suggest a link or article to read about clock generation logic.

For example if I need to generate a Clock of 100Mhz with duty cycle 50%
Click to expand...
Hi ,
In ur testbench file:
1. Selct the time scale to ns
write the foolowing lines :

always
#5 clk = ~clk;
This will generate a clock of 100 Mhz freq and 10 ns time with 50% duty cycle.
regards,
Nishi
 

indeed, For xilinx FPGA's read the clocking resources section of the user guide. look into using the DCM/PLL's for synthesizing clocks from other clocks.

Xilinx does have a goofy guide on generating a ring-oscillator using an IODELAY element. I suggest just using a crystal though.
 

pll is used for generating high frequencies from a very low frequency crystal .
n its available in fpga's u just need to call a inbuilt function to activate pll.
 

You need external oscillator (Crystal) to generate source clock. 100 MHz oscillator is available.

If you want to generate from other clock frequency then use FPGA's inbuilt PLL/DCM.

If you want to generate for the simulation purpose, use time command in your testbench.

hope it helps
 

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