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ATmega16 microcontroller i\o ports rise time, fall time

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M.Husnain

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my target is to achieve the 1 MHz ttl Clk with 5n seconds rise time and fall time.
may kindly inform me the
ATmega16 microcontroller i\o ports rise time, fall time and on time
thankx
 

"""1 MHz ttl Clk with 5n seconds rise time and fall time.""""


Hello Husnain, it is better idea to do this job from FPGA, try a small FPGA, it is not difficult.


Rise / Fall time of clock is mainly dependent upojn I/O Port switching time of FPGA /microcontroller. Search it in device's data sheet. As a rule of thumb rise time/ fall time is 10% of clock cycle period.
 

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