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'low skew rate' and 'programable I/O current'

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ifarmer

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I am wondering how the FPGA realize, not in software but hardware, the function of 'low skew rate' and 'programable I/O current'.

I guess that, for low skew rate function, FPGA adds a capacitive load on the gate of output buffer; for programable i/O current, FPGA parallel connects several buffers.

I know my idea is quite naive. Anybody can give the truth or rative materal in detail. Thanks.

Regards
Ifarmer
 

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