Consideration on power mos layout.

power mos layout

Hi,
Now I am designing a Class-D output amplifier.Its average current is up to 100mA. Moreover, its transient current is as high as 700mA.
I wonder how should I layout it and whether the common ESD protection will work under this condition.

when you design power mos, you design for output resistance usually. for example, a 2 ohm nmos can sink 5A from a 10v rail, but only 0.5A from a 1v rail.

highest layout density is from the waffle layout, but it suffers from early wearout and low esd. (ie-all the right angles cause field concentration and hot carrier/esd weakness)

so my suggestion is : just use straight mosfet layout - that will work just fine. make some calculations of your gate length vs poly resistance to tell you how long you can make a gate before your RC really slows your turn-on characteristic.

an example i just made was a 30v, 1Ohm driver with 4.5um gate length needed for HCI survival at 30v, 45um gate width per device (gives 10 squares per gate at 50mOhm per sq - fast turnon!), merged drain & source, 100 gates per block, and 10 blocks used for the driver. there you go: W/L of 45,000/4.5.. metal 1 ran horizontally, connecting gates and striping drains and sources, m2 ran vertically connecting alll D/S in a block, and m3 ran horizontally summing blocks into giant D/S stripes that connect to LX and GND.

next, power mos don't get esd stuctures (your inductor kick will kill them) - you rely on the huge drain tub to absorb the zap. for gate length less than 1um, you should add setback between the drain and gate to add up to about 1-1.5um including gate length. a 0.5um gate placed right next to the drain contact won't survive 2kv esd zap, but a 0.5um gate placed 1um back from drain side will survive 2kv easily. since only the drain touches the output, source can still rest right at gate


read about merging, etc in hastings' art of analog layout..
hope this helps!