Comment on my delay models in VHDL

Delay models in VHDL

Hi everybody,

Let me know your opinion :!:


entity Delay is

generic ( vartime: integer);
Port ( strobe_delay_in : in std_logic;
strobe_delay_out : out std_logic);
end Delay;

architecture Behavioral of Delay is

begin

strobe_delay_out<= transport strobe_delay_in after vartime;


end Behavioral;


I would like to instantiate this module in different part of my VHDL i can do this :?: :?:

:idea: Inst_delay1: delay PORT MAP(
strobe_delay_in =>DStrue ,
vartime=>35ns,
strobe_delay_out =>DStrue_delay );

:idea: Inst_delay2: delay PORT MAP(
strobe_delay_in =>DStrue ,
vartime=>60ns,
strobe_delay_out =>DStrue_delay );
...........................

regards lease:

Re: Delay models in VHDL

Hi,

with this code, you signal DStrue_delay is driven by two signals, I don't think you can compile this.

try this :

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

Entity trans is
end trans;

architecture behavior of trans is

signal fast : boolean := true;
signal DStrue, DStrue_delay : std_logic := '0';
signal DStrue_fast, DStrue_slow : std_logic := '0';

begin

-- stuimuli for test bench
fast <= transport not fast after 1 us;
DStrue <= transport not DStrue after 100 ns;

-- transport algorithm
DStrue_fast <= transport DStrue after 35 ns;
DStrue_slow <= transport DStrue after 60 ns;
DStrue_delay <= DStrue_fast when fast else DStrue_slow;

end;
:wink: