+ Post New Thread

Results 1 to 8 of 8

- 9th March 2010, 20:26 #1

- Join Date
- Mar 2010
- Location
- Florida
- Posts
- 19
- Helped
- 0 / 0
- Points
- 667
- Level
- 5

## Difference between Divide by n counter and clock dividers

Hi,

I want to know the difference between a divide by 3 or 4 or 5 or watever counter and a clock divider. As of now, I know that a counter begins from an initial value and counts tilll a specified value. A divide by 5 counter counts upto 5 and resets to 0 after 5, then what is the concept of the clock pulse apperaing every five clock cycles and the frequency being divided by 5??? Does the counter divide the clock's frequency or count upto a paricular number in a cycle???????????????

- 9th March 2010, 20:26

- 9th March 2010, 23:26 #2

- Join Date
- Sep 2008
- Posts
- 25
- Helped
- 7 / 7
- Points
- 978
- Level
- 7

## Re: Difference between Divide by n counter and clock divider

the counter just counts. for instance in your example of counting up to five, you'll need a 3 bit counter, then when it reaches the value 3'b101 some combinational logic will go high (output will be a divide by five clock signal with %20 duty cycle) and cause the counter to reset to zero. the master clocks frequency never changes. if you're dividing by a power of two you can just use the MSB of the counter and get a new slower %50 duty cycle clock. eg. the MSB of a 3 bit counter is a square wave toggling at 1/2^3 of the clock signal.

1 members found this post helpful.

- 10th March 2010, 00:24 #3

- Join Date
- Mar 2010
- Location
- Florida
- Posts
- 19
- Helped
- 0 / 0
- Points
- 667
- Level
- 5

## Re: Difference between Divide by n counter and clock divider

Thanks so much!! That helped a lot.. could you also tell me, when we are looking at the circuit, say three D flip flops connected such that Inverted output is connected back to the D input, this is Divide by 8 counter(1/2^3 like you said), Now, I am guessing that the last D flip Flop's output, q3 will give us the clock/(2^3) clock signal continuously, then where do the numbers 0 to 7 appear??? on the lines q0, q1 and q3????

- 10th March 2010, 00:24

- 10th March 2010, 06:14 #4

- Join Date
- Aug 2007
- Posts
- 2
- Helped
- 0 / 0
- Points
- 962
- Level
- 7

## Re: Difference between Divide by n counter and clock divider

can u give me how u connected 3 d flipflops for divide by 8 counter?

is it synchronous or asynchronous..?

- 10th March 2010, 16:14 #5

- Join Date
- Mar 2010
- Location
- Florida
- Posts
- 19
- Helped
- 0 / 0
- Points
- 667
- Level
- 5

## Re: Difference between Divide by n counter and clock divider

Asynchronous, q of one going into D of the next...

- 10th March 2010, 18:46 #6

- Join Date
- Sep 2008
- Posts
- 25
- Helped
- 7 / 7
- Points
- 978
- Level
- 7

## Re: Difference between Divide by n counter and clock divider

shwetha100: what you're describing is called a "shift register" not a counter. you can also divide the clock with the circuit you described, but it will by a %50 div by 6 clock.

the best way to figure out how it works is to to draw the circuit. label all the nodes (d1,q1,d2,q2 keeping in mind that q1 = d2 and so on) if you have n registers then qn will be your output, and draw all the waveforms including the clock. you must pick a beginning state for all of your registers (this will also determine the functionality) say setting them all to zero. so all the q outputs will be zero, and all the d inputs will be zero with the exception of d1, which is 1 because of the feedback inverter. the number of register stages is the number of clock cycles that it takes for that 1 to propagate through the shift register, and similarly, the number of cycles for the 0 to propagate. so in the end this gives you a 1/(2*n) divider not a 1/(2^n) divider.

let me know if that made sense!

Added after 1 minutes:

shwetha100: that's wrong, there's nothing asynchronous in this circuit. everything is happening in sync with the clock.

- 10th March 2010, 20:16 #7

- Join Date
- Mar 2010
- Location
- Florida
- Posts
- 19
- Helped
- 0 / 0
- Points
- 667
- Level
- 5

## Re: Difference between Divide by n counter and clock divider

it is a divide by 8 circuit and not divide by 6, each D flip flop output divides its input clock by 2, meaning, first flop divides the clock by 2 and this is fed to the second flop which divides this by 2, thus the original clock by 4 and the third flop divides this by 2, the original clock by 8... n its asynchronous because the D output of one clock is being fed into the next flops clock input... meaning all the flops are not getting their clock from the same master clock = asynchronous circuit..

- 11th March 2010, 08:25 #8

- Join Date
- Sep 2008
- Posts
- 25
- Helped
- 7 / 7
- Points
- 978
- Level
- 7

## Re: Difference between Divide by n counter and clock divider

shwetha100: i get it know. i think you're talking about a ripple counter as in

http://web.mit.edu/bunnie/www/xi/seminar/slide3.pdf. i was talking intially about a regular counter (simple fsm type where the current state is the counter value) and in my last post was talking about a mobius counter.

there's more than one way to make a counters and clock dividers. if it's the ripple counter then it can be viewed as a counter or a clock divider. i'm not sure if you're original question is answered or not?

+ Post New Thread

Please login