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how to write it in vhdl?

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sandy.vb

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hi
i've got his expression from verilog

a <= {(sig_width+1){'1'}} where sig_width is a parameter.

how do i write the same thing in vhdl?

thanx in advance.
 

Unlike verilog, vhdl is strongly typed, so you can't implicitly define the length of "a" by its assignment. Assuming signal "a" is a vector of defined width sig_width+1 in its declaration then

....
signal a : std_logic_vector(sig_width downto 0);
....
begin
....
a <= (others => '1');
....

"others" applies to all unspecified elements of a vector, so you can also play tricks like

a <= (0 => '0', 1 => '0', others => '1'); to make pattern "111...111100" etc.
 

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