Mixed ground planes: separation, filtering and layout

Mixed ground planes:

Hello,

I'm working on the redesign of a noisy BLDC motor driver. On the same board we have sensitive analog (strain gauge, ADC, etc.), a micro-controller and power MOSFETs. To have a good noise immunity, I want to separate my power and ground planes. I read a lot about signal integrity and PCB design. However, before doing the real board I would like some advice to be sure I'm doing it correctly.

Here is an example schematic:

**broken link removed**

Do you have any comment or suggestion about the way I'm isolating the planes?

Here is the board layout:

**broken link removed**

Note: the real board will be 4-layers Signal|Gnd|Pwr|Signal but to simplify things I routed this example on 2 layers with only a ground plane. On the actual board there will be a power plane superposed on each ground plane.

Am I doing it right?

Thanks in advance for your comments,

JFDuval

Re: Mixed ground planes:

Couple questions for you:
1. +5V and GND are the locations of the noise, yet they are the common reference between dig and analog? Would it make more sense to make the power filters be in series, i.e. RAW->DIG->ANA? (effectively double filtering the analog, still no GND loops.)

2. Swap C4/C6 and swap C7/C9? So that the lowest value (highest freq) cap is closest to the ferrite?

3. Normally your cap topology is best (power thru the pad, separate GND vias.) But with the ferrite for GND too, does it make more sense to route the GND thru the cap pad then to a via to the room's GND plane? (I honestly don't know on this one.)

4. Any reason for not having an additional decoupling cap directly on each IC power input pin?

Re: Mixed ground planes:

Hello,

1. +5V and GND are the locations of the noise, yet they are the common reference between dig and analog? Would it make more sense to make the power filters be in series, i.e. RAW->DIG->ANA? (effectively double filtering the analog, still no GND loops.)

Click to expand...

This is a good idea, I'll think about it on my real design.

2. Swap C4/C6 and swap C7/C9? So that the lowest value (highest freq) cap is closest to the ferrite?

Click to expand...

Or is it better to have the lower value ("fastest" cap) near my electronics parts...?

4. Any reason for not having an additional decoupling cap directly on each IC power input pin?

Click to expand...

This is only an exercise I made to test my understanding. I quickly added an ADC to get some comments about the way I'm separating the grounds (especially under the ADC chip). On my real board I'm filtering a lot near each chip

I'm still willing to get some professionals' advice!

JF

Hi,
The best placement is for your capacitors as follow:
IC, tightest 10n, next 100n & on the board the 10uF...
The idea of placement your noisy load first to power conn is theoretically OK, but you have it in the "same channel" _top strip of PCB,_ where your sensitiver current has to flow too:-((....
I would place the heavy loads GND more downside, then feed over their the plane (eventual splitted) from ADC to the Pwr connector & the yokes, L1..L4, in the near of input connector.....
Bypassing are thigtest to companion ICs to place & every times the higer frequency element (1 or10nF first, than 100 nF & the some uF are no more so relevat for placing, if you have a 4th capacitor as for high current circuits (motor controller) often neede, 1000uF or higher; their place is at switcher tight(PWM FET)
K.