[Help]CMOS comparator design questions.

Hello All,

I have some questions about cmos comparator design.

I need to design a very low power comparator. The Vdd = 3.3V, Midband Gain ~55dB, GBW ~500KHz. The current needs to be as small as possible.

I plan to put the differential pair in subthreshold region and the rest of the transistors in strong inversion or moderate inversion.

My architecture is samilar to a conventional 2-stage design. 1st stage is a PMOS current source. Then there is a PMOS differential pair. Below are NMOS load/current mirrors. 2nd stage is following the 1st stage by a wilson current mirrow. It is a cascode structure with 2 PMOS on top.

I have the following questions.
(1). How to determine the gain bandwidth of a comparator? Since comparator is not compensated...

(2). For my 0.18um process, the minimum transistor width is 220nm. So when I try to set the biasing current to about 300nA and I set my PMOS in saturation (Vgs = 500mV, Vth ~ 450mV), I get a W/L ~0.6.

Then I have to set the W/L = 300n/500n.

Is it acceptable in analog circuit design??

(3). For the NMOS active load devices, in order to bias them in saturation, I also have to make W/L < 1 since the current is very small...

So will this be okay??

thanks for the help.

wandola said:

(1). How to determine the gain bandwidth of a comparator? Since comparator is not compensated...

Click to expand...

Standard ac simulation

wandola said:

(2)... Then I have to set the W/L = 300n/500n.
Is it acceptable in analog circuit design??

(3). For the NMOS active load devices, in order to bias them in saturation, I also have to make W/L < 1 since the current is very small...
So will this be okay??

Click to expand...

Sure; why not?

Sorry for the first question,

What I mean is that how to consider the GBW in the design? Or, how to obtain a mathematical representation for the GBW in comparator design??

I know i can obtain the GBW through ac sim. what I mean in the design factor.

Thanks for your help.

Ciao

GBW practically don't have meaning for comparator.
Typically in spec a delay time for X [mV] input signal is used,- delay is strongly dependent from input signal value.
DC gain is auxiliary parameter,- for comparator 1e3 or 1e7 have a small influence in typical application, You should to provide necessary minimum, defining number of gain stages.