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vhdl fifo ram with two clks - help needed

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saraiust

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vhdl fifo ram with clks

hi
i'm new at vhdl programming, and I want to learn it as possible as I can.

I have to make a FIFO ram, with 2 clks, but I don't know any special thing about 2 clks in one ram,and of curse I have to make a ram with read and write ports, and this one needs 2 clk-- i think --
so can you help me in analyse these programs?:cry:

I am graduating in computer hardware engineering.
 

but with one array, if one port start to write on one address and the other port start to reed that address, what do i have to do then?...
 

saraiust said:
but with one array, if one port start to write on one address and the other port start to reed that address, what do i have to do then?...
Click to expand...

it's the role of the memory controller to ban any read command when there a write command being processing
 

thank you! but this is exactly my problem, cas i dont know how to make a controller... :cry:
 

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