dinesh.4126
Member level 5
vhdl generate state diagram
Hi,
I have wriiten code for uart receiver in vhdl.and i want to see its state diagram.beacuse first of all start with state machine using state diagram in state orcad.because of first time using it.I have no idea how to give this equation in state machine
input_shift <= input_shift(7 downto 1) & rxa_in_delayed;
so can ISE9.1 generate state digram from VHDL code?
can some help me
---------------------------------------------------
if scl_falling_edge then
if input_shift_count = 0 then
read_state <= read_end;
else
input_shift_count <= input_shift_count - 1;
read_state <= read_bit;end if;
--------------------------------------------------------
if I want to implement above using state machine CAD 1)how can I give if input_shift_count conditions inside if scl_falling_edge condition becuase in CAD edit condition it show only conditions and its output,so If you want to use conditions inside conditions that how can I do that?
2)input_shift <= input_shift(6 downto 0) & rxa_in_delayed; how can I implement this in output.
I am just beginer in state CAD state digram might me these lame question.
Can somebody suggest me something upon this.
Hi,
I have wriiten code for uart receiver in vhdl.and i want to see its state diagram.beacuse first of all start with state machine using state diagram in state orcad.because of first time using it.I have no idea how to give this equation in state machine
input_shift <= input_shift(7 downto 1) & rxa_in_delayed;
so can ISE9.1 generate state digram from VHDL code?
can some help me
---------------------------------------------------
if scl_falling_edge then
if input_shift_count = 0 then
read_state <= read_end;
else
input_shift_count <= input_shift_count - 1;
read_state <= read_bit;end if;
--------------------------------------------------------
if I want to implement above using state machine CAD 1)how can I give if input_shift_count conditions inside if scl_falling_edge condition becuase in CAD edit condition it show only conditions and its output,so If you want to use conditions inside conditions that how can I do that?
2)input_shift <= input_shift(6 downto 0) & rxa_in_delayed; how can I implement this in output.
I am just beginer in state CAD state digram might me these lame question.
Can somebody suggest me something upon this.