RollingEEE
Full Member level 3
- Joined
- Mar 25, 2006
- Messages
- 165
- Helped
- 8
- Reputation
- 16
- Reaction score
- 7
- Trophy points
- 1,298
- Location
- Bangladesh
- Activity points
- 2,406
4 bit alu vhdl
This code is suppose to be vhdl for a 4 bit ALU
QuartusII gives error saying that
Please help
This code is suppose to be vhdl for a 4 bit ALU
Code:
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity normalalu is
port (A, B: in std_ulogic_vector(0 to 3);
O : out std_ulogic_vector(0 to 4);
S : in std_ulogic_vector (0 to 1));
end normalalu;
architecture behavior of normalalu is
begin
reg:process(A, B, S)
variable Q: std_ulogic_vector(0 to 4);
begin
if S = "00" then
O(0 to 4)<= A(0 to 3) + B(0 to 3);
elsif S = "01" then
O(0 to 4)<= A(0 to 3) - B(0 to 3);
elsif S = "10" then
O(0 to 4)<= A(0 to 3) and B(0 to 3);
else
O(0 to 4)<= A(0 to 3) or B(0 to 3);
end if;
end process;
end behavior;
QuartusII gives error saying that
Error (10327): VHDL error at normalalu.vhd(17): can't determine definition of operator ""+"" -- found 0 possible definitions[/code]
Please help