Bandgap startup circuit

start up circuit

Hi,

I am trying to make sense out of the startup circuit of this bandgap reference design, but I have not been able to. Could someone please help? [/img]

bandgap startup time -patent

I am also not sure but i see this as since ur op-amp output is given to a inverter like structure any one of them will turn on. this will start pushing current through the PMOS into the bandgap BJT and creating a mismatch in the input of the op-amp forcing it to turn on. the circuit will turn off when the PMOS gate goes high ...

startup bandgap

A simple test, simple to automate, is that your circuit should be enter the normal mode from any node voltage combinations. If you have 9 nodes you have possible 512 states where either VDD or 0 is used as initial state. Some of the state lead to high currents or some very short time responses.

But there are possible states where is takes very long or ever to reach the normal state. That is understand as robustness. You can also check your circuit by hand following this method. There is a further complication that in some situations als offsets play a key role.

If both nodes "x" and "y" are at VDD and the opamp does not have a startup the circuit fails.


That is a classic error. Your startup should generate an independ current which is switched off, or is reduced in impact to accuracy, after the bandgap enters normal mode. The initla current should be high enough so that also an offset on the opamp is tolerable... (that is a an exercise)