How can i realize that the FPGAs configuration is completed?

Hi my friends
I have designed a hardwrae based on Spartan-3A generation, and i use VHDL to programming.

Please tell me how i can realize that the FPGA's configuration is completed an the FPGA is ready to use. i want to use this feature to initialize my internal register by desired values.

Are there any solutions to detect it by hardware or software?
Can i connect the FPGA's PROG_B pin to one of its I/O pins to detect it?

thank you for your attention.

Re: How can i realize that the FPGAs configuration is comple

For XC5202, Spartan, Spartan XL that I've used in the past I'm using to look the DONE pin, when the FPGA is succesfully configured this pin goes to logic high.

Some other info can be found here



Hope it help.

Bye
Pow

Re: How can i realize that the FPGAs configuration is comple

TekUT said:

For XC5202, Spartan, Spartan XL that I've used in the past I'm using to look the DONE pin, when the FPGA is succesfully configured this pin goes to logic high.

Click to expand...

I appreciate you.
please tell me can i connect FPGA's DONE pin to another its I/O pin to detect end of cofiguration in vhdl code and use this I/O like a Reset input?

are there any better solutions?

Re: How can i realize that the FPGAs configuration is comple

I think you can but if I were you I would at least add some delay for the reset signal.

Re: How can i realize that the FPGAs configuration is comple

blitzwing said:

I think you can but if I were you I would at least add some delay for the reset signal.

Click to expand...

Yes of course
I will include a RC network on DONE pin.
See attachment.
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Re: How can i realize that the FPGAs configuration is comple

Mehdi1357 said:

TekUT said:

For XC5202, Spartan, Spartan XL that I've used in the past I'm using to look the DONE pin, when the FPGA is succesfully configured this pin goes to logic high.

Click to expand...

I appreciate you.
please tell me can i connect FPGA's DONE pin to another its I/O pin to detect end of cofiguration in vhdl code and use this I/O like a Reset input?

are there any better solutions?

Click to expand...

Before DONE going high logic inside the FPGA is not working because the programming stage isn't completed, after DONE will go high the FPGA start to work, is better check the DONE pin outside the FPGA and when this is high send, after some time, a reset signal to the selected FPGA input. For example you can use a reset ic (remember also to put a pull-up resistor, 10kOhm, from the DONE pin and the positive supply), or use a simple passive RC network to delay this signal but may be you can see another very important issue, FPGA input have a maximum value for the signal rise time applied to the IO pins for this reason a reset is the best safe solution from my point of view.

Bye
Pow

Re: How can i realize that the FPGAs configuration is comple

Feeding back the DONE signal to an FPGA input to my opinion should be completely unnecessary, cause the code can achieve a defined state after configuration without an external signal. Or isn't this the case with Xilinx FPGA?

Re: How can i realize that the FPGAs configuration is comple

FvM said:

Feeding back the DONE signal to an FPGA input to my opinion should be completely unnecessary, cause the code can achieve a defined state after configuration without an external signal. Or isn't this the case with Xilinx FPGA?

Click to expand...

I don't know there is a software solution to initialize my registers by desired values after configuration process (without RESET input). but i know initial values that loaded in to defined SIGNALs or VARIABLEs when we are defining a SIGNAL or VARIABLE won't be synthesizable in ISE software.they are implemented during simulation process.

do you have a better idea?