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address decoding in vhdl

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brunokasimin

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hello,

I have a soft-core processor and an uart. in order to send the data from output of the processor to the input of uart vhdl module, i'm thinking that i need address decoding to writes the data into uart?? am i right?? but to do the address decoding in vhdl, i dont have any idea how to write it..can someone guide me on how to do this ?? Thx very much
 

If WR and RD are the command of the processor and address it's address bus a simple address decoding is something like this:

write_uart <= ((address = UART_ADDRESS) and (WR='1') and (RD='0'));
read_uart <= ((address = UART_ADDRESS) and (WR='0') and (RD='1'));
 

what interface your UART is having? Well there are different registers (such as status\ data \ baud rate selection etc) which can be selected by address lines...but it depends on particular design...can you post the port map ?
 

i'm using rs232. is that you meant with interface ?? well, this uart i downloaded from opencores.org. about port map, there is no port mapping in the uart..i attached along my uart module in vhdl
 

It is a nicely documented uart.
You should instantiate this UART as a component in your higher level module.


Code: 
these ports can be connected to cpu.

    rx_data_out    : out std_logic_vector(7 downto 0);   -- Received Data
    rx_data_en     : out std_logic;            -- Received data enable control signal
    rx_ovf_err     : out std_logic;             -- Received data over frame error detected
    rx_parity_err  : out std_logic;            -- Received data parity error
    tx_data_in     : in  std_logic_vector(7 downto 0);   -- Transmited data 
    tx_data_en     : in  std_logic;                      -- Transmited data latch enable
    tx_ch_rdy      : out std_logic;                      -- Transmition channel ready status signal

-- Control signals ....these you can give directly...e.g. you want odd parity set parity_type as one in vhdl..
baud_sel       : in  std_logic_vector(3 downto 0);   -- Baud rate value see Note   
    parity_en      : in  std_logic;                      -- Enable parity control signal active HIGH
    parity_type    : in  std_logic);                     -- 1:ODD parity / 0:EVEN parity 
end entity;


These two signal are RS232 I/O interface.

  rx_data_serial : in  std_logic;          -- Received Serial data from RS232(RxD line)
  tx_data_serial : out std_logic;          -- Transmited Serial data to RS232(TxD line)
 

hello,
you can find my cpu processor in attachment
thx for the reply..here i attach my soft-core processor for cpu...mem_writ is my data output and out_mem_addr is the address

mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);

wordSize =32
maxAddrBitIncIO = 14


how to decode this address out_mem_addr???
how to build address decoder in vhdl?? i'm very inexperienced on this

thx
 

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