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- 9th October 2007, 07:20 #1

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## fifo depth calculation

A FIFO has following data rate. What is depth of that?

incoming data = 80 words at 100 clks

outgoing data = 8 words per 10 clks

read clk = write clk

fifo data width = 1 word.

What is the fifo width for this configuration?

- 9th October 2007, 07:44 #2
## fifo depth question

Before going to the fifo width portion, can you tell me how 8 words are written in 10 clock cycles? is there any latency involved ?

from what i can see, 8 words in 10 clock cycles and 80 words in 100 clock cycles are the same, only difference might be the delay involved.

correct me if i'm wrong.

- 9th October 2007, 07:57 #3

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## fifo size calculation

no delays are mentioned. But, as it is a asynchronous FIFO, read and write clks are not same(not in phase)...so FIFO is required. Need to calculate its depth.

- 9th October 2007, 07:57

- 9th October 2007, 08:35 #4

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## calculating fifo depth

Hi ppallavi:

a few days ago,i also have the same question, shavakmm give me the answer which calculate the depth of FIFO ,the link is as follows,you can see it

http://www.edaboard.com/ftopic274981.html

BR.

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- 9th October 2007, 09:36 #5

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## calculate fifo depth

hi pallavi.

u see the asic-world.com site is there fifo depth calculation

vamsi

- 10th October 2007, 05:23 #6

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## asynchronous fifo depth calculation

What is the answer of the question? there is no burst mentioned..

- 10th October 2007, 11:56 #7
## asynchronous fifo depth calculation burst rate

why don't you get more info about ur FIFO

or try to match the one here to the equation given by the other post :)

- 10th October 2007, 12:13 #8

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## asynchronous fifo depth

Hi PPallavi,

In this there are two cases we have to consider in determing the depth,

1)Best case: The incoming data is 80words /100clk i.e the data starts writing for 80clks and remains idle for 20clks.

In this case for reading 80 words at the rate 8 words/10clks requires 100clks. so, the fifo size is 20words.

2)worst case: The incoming data idle for 20clk and starts writing at 20th clk onwords and second write starts with 101th clk completes writing at 180th clk and idle upto 200th clk, hence in this case there are total 160words write in 200clk.

But read starts from 20th clock and completes at 220th clk, hence in this case the fifo size is 40.

so, the answer is 40.

If its wrong kindly corect it.

Thanks and Regards

satyakumar

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- 14th October 2007, 17:39 #9

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## calculation of fifo depth

The answer is 32.

Consider the below mentioned case.

Read Window

<---80---><---20---><----20---><---80---->

80 read followed by 20 empty cycles.

20 empty cycles followed by 80 read cycles.

Max writes can happen in this (20 + 20 ) cycles window is 8 x 4 = 32 .

- 15th October 2007, 07:39 #10

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## how to consider a fifo depth

Hi ,

Thank you for the reply.

Can you please elaborate "8x4 = 32 " part in the reply.

Thanks.

- 15th October 2007, 07:39

- 15th October 2007, 11:09 #11

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## fifo depth rules

@sanjay11

Here read is 8 words per 10 clks, So, you must have to spend 2 idle cycles/10 clk cycles, i.e. you can not read continuosly for 80 cycles and spend 20 idle cycles later...

Worst write can be as follows: (Just creating a diagram from, what satyakumar has mentioned)

<-20-><-80->|<-80-><-20->

First burst | second burst

Here, effective writing is only for 160 clock cycles, So worst write is 160 words/160 clks.

Now, Read speed is 8 words/ 10 clk cycles.

So, in 160 (16 * 10) read clk cycles, we can read 128(16 * 8 ) words. reamaining words we need to store in fifo. that is 32(160 - 128).

So, I guess fifo depth need to be**32**only...

Please, let me know if this calculation is wrong.

Correction is always invited :D

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- 16th October 2007, 08:52 #12

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## fifo depth calculations

Hi bharat_in,

sorry, I misinterpreted the problem,

my understanding was 8/10 is write ratio,

and 80/100 is read ratio.

but even in this case depth is 32, as you said.

<----Incoming data stream worst case-->

<--20--><--80--><--80--><--20-->

<Empty><----Data------><Empty>

Worst case is 160 clocks continuous incoming data.

For everyoutgoing 10, accumulation of 2 happens.

max that can go out is 16 x 2 = 32.

Sorry for my mistake.

- 16th October 2007, 10:06 #13

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## fifo question 80/100 8/10

Hi,

One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Statistically, Data rate varies in the system majorily depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.

For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered.

So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.

So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.

In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.

So following up with the equation as explained below: Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).

Here we have not considered the sychnronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.

Example : FIFO Depth Calculation

Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,

A synchronized fifo

Writing clock 30MHz - F1

Reading clock 40MHz - F2

Writing Burst Size - B

Case 1 : There is 1 idle clock cycle for reading side - I

Case 2 : There is 10 idle clock cycle for reading side - I

FIFO depth calculation = B - B *F2/(F1*I)

If if we have alternate read cycles i.e between two read cycle there is IDLE cycle.

FIFO depth calculation = B - B * F2/(F1*2)

In our present problem FIFO depth = B - B *40/(30*2)

= B(1-2/3)

= B/3

That means if our Burst amount of data is 10 , FIFO

DEPTH = 10/3 = 3.333 = 4 (approximatly)

If B = 20 FIFO depth = 20/3 = 6.6 = 7

or 8 (clocks are asynchronous)

If B = 30 FIFO depth = 30/3 = 10

10+1 = 11 (clocks are asynchronous)

If 10 IDLE cycles betweeen two read cycles .

FIFO DEPTH = B - B *F2/(F1*10) .

= B(1-4/30)

= B * 26 /30

Added after 24 seconds:

Hi,

One of the most common questions in interviews is how to calculate the depth of a FIFO. Fifo is used as buffering element or queueing element in the system, which is by common sense is required only when you slow at reading than the write operation. So size of the FIFO basically implies the amount of data required to buffer, which depends upon data rate at which data is written and the data rate at which data is read. Statistically, Data rate varies in the system majorily depending upon the load in the system. So to obtain safer FIFO size we need to consider the worst case scenario for the data transfer across the FIFO under consideration.

For worst case scenario, Difference between the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered.

So in the question itself, data rate of read operation is specified by the number of idle cycles and for write operation, maximum data rate should be considered with no idle cycle.

So for write operation, we need to know Data rate = Number of data * rate of clock. Writing side is the source and reading side becomes sink, data rate of reading side depends upon the writing side data rate and its own reading rate which is Frd/Idle_cycle_rd.

In order to know the data rate of write operation, we need to know Number of data in a Burst which we have assumed to be B.

So following up with the equation as explained below: Fifo size = Size to be buffered = B - B * Frd / (Fwr* Idle_cycle _rd ).

Here we have not considered the sychnronizing latency if Write and Read clocks are Asynchronous. Greater the Synchronizing latency, higher the FIFO size requirement to buffer more additional data written.

Example : FIFO Depth Calculation

Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth,

A synchronized fifo

Writing clock 30MHz - F1

Reading clock 40MHz - F2

Writing Burst Size - B

Case 1 : There is 1 idle clock cycle for reading side - I

Case 2 : There is 10 idle clock cycle for reading side - I

FIFO depth calculation = B - B *F2/(F1*I)

If if we have alternate read cycles i.e between two read cycle there is IDLE cycle.

FIFO depth calculation = B - B * F2/(F1*2)

In our present problem FIFO depth = B - B *40/(30*2)

= B(1-2/3)

= B/3

That means if our Burst amount of data is 10 , FIFO

DEPTH = 10/3 = 3.333 = 4 (approximatly)

If B = 20 FIFO depth = 20/3 = 6.6 = 7

or 8 (clocks are asynchronous)

If B = 30 FIFO depth = 30/3 = 10

10+1 = 11 (clocks are asynchronous)

If 10 IDLE cycles betweeen two read cycles .

FIFO DEPTH = B - B *F2/(F1*10) .

= B(1-4/30)

= B * 26 /30

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- 17th October 2007, 05:27 #14

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## depth of fifo problems

more information on

http://www.asic-world.com/tidbits/fifo_depth.html.

a great website for beginners.

- 17th October 2007, 13:48 #15

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## determine depth of fifo

Let us consider your case:

incoming data = 80 words at 100 clks

outgoing data = 8 words per 10 clks

read clk = write clk

While calculating depth of fifo, we need to consider the worst case. So assume that first 20 clks are idle i.e there is no write into fifo.write is started from 21st clk and 80 words are written continuously into fifo till 100th clk.

Read also started from 21st clk with 8 words per 10 clks. So maximum 64 words can be read till 100th clks so (80 - 64 = 16) are left over without read.

Hence the fifo depth is 16.

- 29th October 2007, 14:45 #16

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## calcualting fifo depth

16 is not correct answer.

- 29th October 2007, 16:49 #17

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## calculating asynchronous fifo depth

It's 32.

Since you didn't specify duty cycle, the worst case condition is two 80-word writes back-to-back on the write side. That is:

<20 cycles idle> <80 cycles write> <80 cycles write> <20 cycles idle>

This means that 160 writes will occur consecutively. Assuming read begins at the same time as write begins (ignoring logic and control delays), the read side will be able to read (160/10)*8 = 128 words in that 160 cycles time (reading 8 words per 10 cycles). The timing looks like:

Write side: < 10 writes > < 10 writes > < 10 writes > ...

Read side: <8 reads><2 idle> <8 reads><2 idle> <8 reads><2 idle> ...

This means that at the end of the 160 cycle burst, there will be 160-128 = 32 words left over in the FIFO to read. Your FIFO will need to be 32 words deep.

- 21st June 2008, 11:55 #18

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## case depth calculation

Finally which answer is correct...........

Any wayz..........Thanks alot for ur precious time.

- 25th June 2008, 10:19 #19

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## asynchronous fifo length calculation

I also think 32 is the answer.

- 27th June 2008, 03:49 #20
## async fifo depth

Hi Pallavi,

I am attaching a PDF file.. Plz go through this.. I think it will solve your basic doubts

Thanks,

sp3

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