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    How to write a Delay code in VHDL ?

    Hello,

    could you help me plz?

    I want an example in order to understand how I can write a Delay code in VHDL.

    Thank you in advance!!!!

    •   Alt8th September 2007, 11:45

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    delay vhdl

    what do you mean by delay... do you want to write a test bench... or you want a module which delays a signal... 9if you want to write a test bench then you can use
    wait for 50ns;command...
    be clear wth your question....



    •   Alt8th September 2007, 13:11

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    vhdl delays

    in vhdl there are three delays are defind....
    1. Inertial delay.
    2. Transport Delay
    3. Reject Delay

    you can refer to the books for detail.



    •   Alt8th September 2007, 13:55

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    vhdl synthesizable delay

    Quote Originally Posted by BooM
    Hello,

    could you help me plz?

    I want an example in order to understand how I can write a Delay code in VHDL.

    Thank you in advance!!!!

    Delay is modeled by WAIT statement in VHDL .. but keep in mind that it's not synthesizable .. on the other hand, you can model a delay of one-clock cycle by designing a flip flop (synthesizable) ..



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    vhdl delay code

    Thank you guys for your replies!

    I didn't know that there are 3 delay...So I will check to references.



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    delay in vhdl

    You can use for loop to generate a delay based on the crystal frequency.



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    vhdl delay syntax

    Another possibility:
    Some FPGAs provide special time delay features, such as the adjustable IODELAY in a Virtex-5 I/O block. To use this special hardware delay, you must instantiate a special Xilinx module. The synthesis tools won't infer the delay from conventional HDL delay syntax.



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