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Latched Comparator design for high-speed applications

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mickey_melomane

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Hi... I am currently workin on a latched comparator design for an ADC... I aint able to relate the dc parameters to its performance in terms of kickback and offset...

I used six preamplifier stages, but my design fails the Monte Carlo analysis... ie. My latch does not serve its purpose...
I noticed that the last stage of preamp, produces a different bias voltage at its ouput in its differential arms... Is there any method to make the dc voltage in two arms at output of a diode load opamp equal...???


Sidharth
 

I also meet the same problem, which guy can give an answer?????
 

Difficult know w/o circuit schematics...
if enough pre-amp gain, latch offset not problem.
post schematic please.
 

i am also having same problem , help me out
 

I agree with ch1k0 please post your schematic, even an abstracted one, then we can see but i think there is a solution.

thanks,
Reagrds
 

hi , what about a schmeatic ?
 

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