trashbox
Advanced Member level 4
Hi guys,
I have two questions about PLL design,would you please give me any comments?
1.PLL jitter issue
I want to get a low jitter clock with a range from 50MHz to 200MHz. There are two selections: a)let vco have a small gain (gain=Kvco=df/dv) by kinds of techniques such as multi F-V curve because the VCO noise is proportional to the Kvco. b)let vco oscillate at double frequency (from 100MHz to 400MHz) and then use divider-by-2 to get the target frequency range (from 50MHz to 200MHz). The advantage is: the high frequency has smaller absolute jitter (suppose the percent=jitter/period is equal almost at low and high frequency), the signal after div-2 has smaller jitter if the div-2 do not introdule more noise. The disadvantage is the VCO has bigger Kvco this method.
I am not sure which method is better in this case?
2.Power noise issue
In a very large SOC system such as CPU or GPU, the digital parts will introduce noise into analog parts by kinds of mechanisms even though many skills have been used such as guard ring. My question is: compared with analog mos's noise (thermal noise and flick noise) itself, who is the dominant noise source, noise from digital parts or mos itself in analog parts?
Thanks very much.
I have two questions about PLL design,would you please give me any comments?
1.PLL jitter issue
I want to get a low jitter clock with a range from 50MHz to 200MHz. There are two selections: a)let vco have a small gain (gain=Kvco=df/dv) by kinds of techniques such as multi F-V curve because the VCO noise is proportional to the Kvco. b)let vco oscillate at double frequency (from 100MHz to 400MHz) and then use divider-by-2 to get the target frequency range (from 50MHz to 200MHz). The advantage is: the high frequency has smaller absolute jitter (suppose the percent=jitter/period is equal almost at low and high frequency), the signal after div-2 has smaller jitter if the div-2 do not introdule more noise. The disadvantage is the VCO has bigger Kvco this method.
I am not sure which method is better in this case?
2.Power noise issue
In a very large SOC system such as CPU or GPU, the digital parts will introduce noise into analog parts by kinds of mechanisms even though many skills have been used such as guard ring. My question is: compared with analog mos's noise (thermal noise and flick noise) itself, who is the dominant noise source, noise from digital parts or mos itself in analog parts?
Thanks very much.