+ Post New Thread
Results 1 to 8 of 8

22nd November 2006, 05:25 #1
 Join Date
 May 2004
 Posts
 227
 Helped
 1 / 1
 Points
 2,935
 Level
 12
vhdl addition
Hi Guys
Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."
[syntax=vhdl]
Library IEEE;
Use Ieee.std_logic_1164.all;
entity add is
Port(
a: in std_logic_vector(3 downto 0) ;
sum:out std_logic_vector(3 downto 0)
);
end add;
architecture behav of add is
signal tmp : std_logic_vector(3 downto 0);
begin
tmp <= a(0) + a(1) +a(2) + a(3) when en = '1' else "0000";
sum <= tmp;
end behav;[/syntax]Last edited by andre_teprom; 4th March 2014 at 02:20. Reason: added VHDL syntax formatting

22nd November 2006, 05:25

22nd November 2006, 07:50 #2
 Join Date
 May 2004
 Location
 Ukraine> S.Korea
 Posts
 18
 Helped
 7 / 7
 Points
 1,700
 Level
 9
addition in vhdl
Hi!
Just add:
1. Use Ieee.std_logic_unsigned.all;
2. en: in std_logic;
3. you have to extend a(0), a(1) etc to 4bit by "000"&
Have a nice day!
Code:Library IEEE; Use Ieee.std_logic_1164.all; Use Ieee.std_logic_unsigned.all; entity add is Port( a: in std_logic_vector(3 downto 0) ; en: in std_logic; sum:out std_logic_vector(3 downto 0) ); end add; architecture behav of add is signal tmp : std_logic_vector(3 downto 0); begin tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000"; sum <= tmp; end behav;

22nd November 2006, 10:51 #3
 Join Date
 May 2004
 Posts
 227
 Helped
 1 / 1
 Points
 2,935
 Level
 12
vhdl std_logic_vector addition
Originally Posted by dunets
Thanks a lot for your help.
tama

22nd November 2006, 10:51

25th November 2006, 05:45 #4
 Join Date
 Nov 2006
 Posts
 9
 Helped
 3 / 3
 Points
 1,140
 Level
 7
vhdl binary addition
Originally Posted by s3034585
include the foolowing libraries
arith and unsigned too then they will executed

26th November 2006, 07:35 #5
 Join Date
 Mar 2005
 Posts
 129
 Helped
 5 / 5
 Points
 2,031
 Level
 10
addition vhdl
i prefer the numeric lib instead of arth lib, the latter is synopsys prepoerity.

2nd March 2014, 08:44 #6
 Join Date
 Mar 2014
 Posts
 16
 Helped
 0 / 0
 Points
 146
 Level
 1
Re: how to go Binary addition in vhdl with vectors
can someone please explain to me what this does ("0000"&a(0)) in this particular line of text below. the exact code is in one of the replies on this thread
Code:tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000"; sum <= tmp;

2nd March 2014, 08:44

2nd March 2014, 12:42 #7
 Join Date
 Jun 2010
 Posts
 6,486
 Helped
 1891 / 1891
 Points
 35,434
 Level
 45
Re: how to go Binary addition in vhdl with vectors
It creates a vector. a(0) is a single bit. Only vectors of type signed or unsigned can be added together.

2nd March 2014, 13:09 #8
 Join Date
 Jan 2008
 Location
 Bochum, Germany
 Posts
 41,510
 Helped
 12665 / 12665
 Points
 239,577
 Level
 100
Re: how to go Binary addition in vhdl with vectors
The code calculates the number of '1' bits in input vector a. Is this what you want to achieve?
The question title might suggest that you want to add multiple vectors. But there's only one input vector.
+ Post New Thread
Please login