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a problem in simulation VHDL code

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snowlandeg

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salam ,,,

this is a VHDL code for generating a 10 sec pulse in for every minute


Entity T2 is
port ( clk : in std_logic ;
T : out std_logic );
end entity ;
architecture behv2 of T2 is
begin
process ( Clk )

variable PCount : Integer :=0 ;
variable SecCount : Integer := 0 ;
variable PC : Integer :=0 ;
variable SecC : Integer := 0 ;
begin
L1 : for PC in 0 to 24999999 loop
if (clk'event and clk = '1') then
PCount := PCount + 1 ;
if PCount = 24999999 then
SecCount := SecCount + 1 ;
end if ;
end if ;
end loop L1 ;
L2 : for SecC in 0 to 59 loop

if SecCount > 0 and SecCount < 10 then
T <= '1' ;
else T <= '0' ;

end if ;

end loop L2 ;
end process ;
end behv2 ;

the problem is when I start simulation in modelsim it goes so slowwwwwww


could any body help me fixing this problem

thanks in advance ,,,,

note " we need synthesible code "
 

What version of Modesim are you using? The default resolution Modelsim uses is 1 picosecond, so any simulation of a minute requires an enormous amount of clock cycles. This resolution can be changed. Also, this will syntesize using a 25 bit counter, which can be hard to route with a 25MHz clock (depends on the device you are using). It may be better to divide down the clock using a linear feedback shift register to get 1 second pulses.
 

salam ,,,
thanks for concern nand_gates


the clock may be 4 MHz

but I try it on any frequency

does the code do the function we need ?

Added after 38 minutes:

salam,,,

thanks MWind


I'm using ModelSim 6c version
Also, this will syntesize using a 25 bit counter, which can be hard to route with a 25MHz clock (depends on the device you are using). It may be better to divide down the clock using a linear feedback shift register to get 1 second pulses
Click to expand...

I need more clarication
 

Conventional binary counters use complex or wide fan-in
logic to generate high end carry signals. A much simpler
structure sacrifices the binary count sequence, but
achieves very high speed with very simple logic, easily
packing two bits into every CLB. Such Linear Feedback
Shift-Register (LFSR) counters are also known as pseudorandom
sequence generators. see XAPP052 from Xilnx. I use this approach when I need a large clock division (i.e. 1 second clock from a 25Mhz clock). Create another process to toggle a signal on the 1 second clock pulse.
 

use an integer counter to count every rising edge of ur clk frequency... if one counter if not enuff (integer values overflow), then use double counter to loop... untill it reaches one minute... this can b done easily wth mathematic..

after that, make the output high for 10s (wth the same approach, use counter on rising edge)... then go to the first one... loop for another one min...

shouldnt b hard, just tht i am kinda busy... so can only tell u how to do it...

regards,
sp
 

thanks for all people replies on this topic


does the problem is in the for loop statement and the senstivity list as it repeats the same part for ever ???!!
 

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