shaiko
Advanced Member level 5
VHDL procedure that simulates the lock function of a PLL
Hello,
I'm trying to write a procedure that will simulate a clock.
If reset is asserted, the clock output should be '0' and so it the lock signal.
If reset isn't de-asserted, the lock signal should rise and the clock should start to oscillate after a certain time.
This is what I wrote so far:
Unfortunately it doesn't work.
The clock output is a stable 'U'.
What's wrong?
Hello,
I'm trying to write a procedure that will simulate a clock.
If reset is asserted, the clock output should be '0' and so it the lock signal.
If reset isn't de-asserted, the lock signal should rise and the clock should start to oscillate after a certain time.
This is what I wrote so far:
Code:
procedure clock_generation
(
constant frequency : real ;
constant time_lock : time ;
signal reset : in std_logic ;
signal clock : out std_logic ;
signal lock : out std_logic
) is
constant high_time : time := 0.5 sec / frequency ;
variable low_time : time ;
begin
low_time := 1 sec * ( 1.0 / frequency ) - high_time ;
clock <= '0' ;
lock <= '0' ;
if reset = '1' then
clock <= '0' ;
lock <= '0' ;
else
wait for time_lock ;
lock <= '1' ;
loop
wait for low_time ;
clock <= '1' ;
wait for high_time ;
clock <= '0' ;
end loop ;
end if ;
end procedure ;
;
The clock output is a stable 'U'.
What's wrong?