wtr
Full Member level 5
If I was in Verilog I could do
`include "my_defines.sv"
My defines could have multiple includes to other snippets of code. The nature of Verilog compilers allow these various includes to be pulled into the current file I'm compiling.
!!!!!!!!!!!!!!!!!!!
Now I'm curious if I can do something similar in VHDL land.
For example
RTL code
`include "my_defines.sv"
My defines could have multiple includes to other snippets of code. The nature of Verilog compilers allow these various includes to be pulled into the current file I'm compiling.
!!!!!!!!!!!!!!!!!!!
Now I'm curious if I can do something similar in VHDL land.
For example
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 package word_type_pkg is -- Declarations constant c_nible_size : integer := 4; constant c_byte_size : integer := 8; constant c_word_size : integer := 16; constant c_dword_size : integer := 32; constant c_qword_size : integer := 64; constant c_oword_size : integer := 128; subtype nible_t is std_logic_vector(c_nible_size - 1 downto 0); subtype byte_t is std_logic_vector(c_byte_size - 1 downto 0); subtype word_t is std_logic_vector(c_word_size - 1 downto 0); subtype dword_t is std_logic_vector(c_dword_size - 1 downto 0); subtype qword_t is std_logic_vector(c_qword_size - 1 downto 0); subtype oword_t is std_logic_vector(c_oword_size - 1 downto 0); end package word_type_pkg;
Code VHDL - [expand] 1 2 3 package other_pkg is -- stuff end package other_pkg;
Code VHDL - [expand] 1 2 3 4 5 6 7 use x.word_type_pkg.all; use t.other_pkg.all; package combined_pkg is -- -- use the other package end package;
RTL code
Code VHDL - [expand] 1 2 3 4 5 6 library ieee; use ieee.std_logic_1164.all; library generics; use generics.combined_pkg.all; entity ...