tanish
Junior Member level 2
hello.
I try to implement a distributed RAM using ISE IP core generator but I have this warning:
WARNING:HDLCompiler:1499 - "E:\M.Sc\ISE projects\ipcore-test\test2\ipcore_dir\myram.v" Line 39: Empty module <myram> remains a black box.
my verilog code is :
I used .veo file to instantiate myram.
and myram.v file that has been made by core generator is :
could anyone tell me exactly what the problem is?
when I try this method on a simple 6bit adder everything is ok.
I try to implement a distributed RAM using ISE IP core generator but I have this warning:
WARNING:HDLCompiler:1499 - "E:\M.Sc\ISE projects\ipcore-test\test2\ipcore_dir\myram.v" Line 39: Empty module <myram> remains a black box.
my verilog code is :
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 module test2( data_in, clock, wen, ce, addr, data_out ); input [15:0]data_in; input clock; input wen; input ce; input [5:0]addr; output [15:0]data_out; myram a1 ( .a(addr), // input [5 : 0] a .d(data_in), // input [15 : 0] d .clk(clock), // input clk .we(wen), // input we .i_ce(ce), // input i_ce .spo(data_out) // output [15 : 0] spo ); endmodule
I used .veo file to instantiate myram.
and myram.v file that has been made by core generator is :
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 `timescale 1ns/1ps module myram( a, d, clk, we, i_ce, spo ); input [5 : 0] a; input [15 : 0] d; input clk; input we; input i_ce; output [15 : 0] spo; // synthesis translate_off DIST_MEM_GEN_V7_2 #( .C_ADDR_WIDTH(6), .C_DEFAULT_DATA("0"), .C_DEPTH(64), .C_FAMILY("spartan6"), .C_HAS_CLK(1), .C_HAS_D(1), .C_HAS_DPO(0), .C_HAS_DPRA(0), .C_HAS_I_CE(1), .C_HAS_QDPO(0), .C_HAS_QDPO_CE(0), .C_HAS_QDPO_CLK(0), .C_HAS_QDPO_RST(0), .C_HAS_QDPO_SRST(0), .C_HAS_QSPO(0), .C_HAS_QSPO_CE(0), .C_HAS_QSPO_RST(0), .C_HAS_QSPO_SRST(0), .C_HAS_SPO(1), .C_HAS_SPRA(0), .C_HAS_WE(1), .C_MEM_INIT_FILE("no_coe_file_loaded"), .C_MEM_TYPE(1), .C_PARSER_TYPE(1), .C_PIPELINE_STAGES(0), .C_QCE_JOINED(0), .C_QUALIFY_WE(0), .C_READ_MIF(0), .C_REG_A_D_INPUTS(1), .C_REG_DPRA_INPUT(0), .C_SYNC_ENABLE(1), .C_WIDTH(16) ) inst ( .A(a), .D(d), .CLK(clk), .WE(we), .I_CE(i_ce), .SPO(spo), .DPRA(), .SPRA(), .QSPO_CE(), .QDPO_CE(), .QDPO_CLK(), .QSPO_RST(), .QDPO_RST(), .QSPO_SRST(), .QDPO_SRST(), .DPO(), .QSPO(), .QDPO() ); // synthesis translate_on endmodule
could anyone tell me exactly what the problem is?
when I try this method on a simple 6bit adder everything is ok.