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Code VHDL - [expand] 1 2 3 4 5 function "sra" (l : signed; r : natural) return signed is alias l_a : signed(l'length-1 downto 0) is l; begin return resize(l_a, l_a'length + r)(l_a'length+r-1 downto r); end function "sra";
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity shift is Port ( din : in STD_LOGIC_VECTOR(7 downto 0); clk : in STD_LOGIC; dout : out STD_LOGIC_VECTOR(7 downto 0)); end shift; architecture Behavioral of shift is SIGNAL s1,s2 : SIGNED(7 downto 0); begin Process(clk) VARIABLE v1 : SIGNED(7 downto 0); BEGIN IF clk'event and clk = '1' then s1 <= signed(din); s2 <= s1 sla 2; dout <= std_logic_vector(s2); END IF; END PROCESS; end Behavioral;
Am I making any mistake while using sla or it is still not supported in VHDL-2008?ERROR:HDLParsers:808 - Line 19. sla can not have such operands in this context.
I am actually working on Xilinx ISE 14.2.I assume this is Vivado?
when I try this,you're using sla - this is identical in functionality to sll for signed. So use SLL instead.
which is a positive number!!x = 11001010;
y = x sll 2;
y =00101000;
I needed to use both sla and sra. Then I can use the function you provided above for sra and sll for sla.