mahmood.n
Member level 5
I use a reset (rst) signal to first disable a write enable (we) signal and then upon a condition, the 'we' signal will later become active.
testbench:
detector:
writer :
In the simulation with activehdl, I see that 'we' (in the testbench) is first set to U and then X. I can not figure out why. At least the 'r' signal is initially set to '1' and 'we' should be '0' according to the process.
Can someone shed light on that?
testbench:
Code:
architecture myarch of big_design_tb is
component detector port( ..., clk: in std_logic; rst: in std_logic; we: out std_logic);
end component;
component writer port( ..., clk: in std_logic; oe: in std_logic );
end component;
signal r: std_logic := '1';
signal clk: std_logic := '0';
signal we: std_logic;
begin
u2: detector port map( ..., clk, r, we );
u3: writer port map( ..., clk, we );
process( clk )
begin
clk <= not clk after 2 ns;
end process;
process
begin
r <= '0';
a <= 4; -- some inputs
wait for 4 ns;
...
end process;
end
detector:
Code:
port( ..., rst: in std_logic; we: out std_logic);
...
...
process( rst )
begin
if rst = '1' then
we <= '0';
end if;
end process;
process( clk ) -- clk is in the port list
begin
if (clk'event and clk = '1') then
q <= mout; -- these are OK!
if count = 1 then
we <= '1'; -- this is where 'we' is activated
end if;
end if;
end process;
writer :
Code:
port( ..., oe: in std_logic );
...
...
process( clk )
begin
if (clk'event and clk = '1' and oe = '1') then
if (count < n) then
z <= a(0); -- sending the detected value to the output which is OK
end if;
end if;
end process;
Can someone shed light on that?
Last edited: