gain drop following RC extraction 0.18um CMOS XFAB

Hello all,

I have designed a Class AB amplifier, schematic level simulations suggested a gain of 93dB, yet after parasitic RC extraction with Quantus PVS, post-layout simulations suggest 10dB less gain. Do you have any insight what might be the reason? There is no gain drop if the extraction is C only. Which may suggest it has something to the with a parasitic resistance deteriorating the performance. But I tried my best to come up with a decent layout. Used interdigitized current mirrors and input pair for better matching etc. After the simulation, I am checking the DC operating points, for some reason it only shows the unit transistors values (say, if a certain transistor is fingered 30 times, i can see the current, gm etc of one only). But if I multiply the value, the total gm, current etc seems like in good agreement with the simulations. So that leaves me thinking. Any ideas? Thanks in advance.

You could look through the extracted SPICE netlist and
see what values of parasitic R look like. Could be there
is some path that uses a (say) P+ region that's seen as
a "short" by regular extract but a significant R, maybe
an unmatched R, in RC extract.

If you had the time, you could edit the netlist (presumably
not that huge for a single amplifier) knocking down the
parasitic R values one by one (maybe starting with the
largest) while leaving the explicit resistors (if any) alone
until you find one(s) that makes a significant difference.
Then, on to "why?". Brute force, but it's an attack at the
problem.

My best guess is a series resistance at the source of a common source stage, or significant I*R drop where you set the voltage difference for the N & PMOS gates.

This is a typical example where you have to find it. Freebird's suggestion is the usual way. Most designers have a feeling what resistance is too much just by looking at the parasitic file. Or you could just add 10-50 Ohms to different nodes to see which one is the most sensitive one. Most probably the culprit hides there.

Usually, RC-extracted post-layout netlists are huge in size, with thousands (or tens of thousands or hundred of thousands) of parasitic R and C elements, so debugging and analyzing manually these netlists is not a fun.

There are EDA tools that let you calculate effective resistance (from port to instance pins, or between instance pins) based on extracted netlist, so you can plug in these few R values in schematic simulation and see what's the root cause of your problem.
Also, these tools can help you quickly understand where (x, y, z) the problems are coming from.

This sort of analysis is especially useful for advanced nodes, with high R and C parasitic values, and huge number of parasitic elements...

Max

Setting the R, C "filter" limits appropriately can really cut
down on the netlist bloat / clutter. This wants some user
judgment. Like if FET Cdg numbers are in the tens of fF,
let the extraction "discard" any parasitics below 1fF. For
resistors, maybe ditch anything less than 10 ohms if you
are operating at 100uA bias current (that'd be a 1mV
error term, less than natural mismatch). Scale to suit.

You could experiment with these "ignore <" limits
starting from large enough that you get no rPar,
cPar elements added at all, and dial down by decades
until you start to see a manageable sized list of
"suspects". Bearing in mind that these all depend a
lot on their electrical context, whether they're "shady"
or "guilty".

You could also look at the form of the extracted
parasitics' "element card" in the netlist, and grep >
text file, import to Excel, sort on value and "let the
cream rise to the top".

This is a dangerous thing to do, and I would advise against doing this.
Filtering out small parasitic elements often leads to simply ignoring them.
As an example, if you set R filtering at 10 Ohm, all resistors below 10 Ohm will get shorted - which, obviously, can lead to huge inaccuracies in R extraction.
Say, 100 resistors 9 Ohm each in series would give you zero effective extracted resistance resistance for such an extraction setting.

The problem is that both for R and C, many small value elements add up to give large effective parasitic value, and there is not much you can do to resolve that.
It's simply accuracy vs netlist size tradeoff.
You cannot and should not ignore small R and C values, if you need accuracy.

I stand by my suggestions as a practical approach to
the stated problem. Preaching about general hygiene
offers nothing of the sort.

What can one gain of having millions of resistors and caps? The simulation results will be more accurate for sure, but it does not help to answer the question how to modify the layout to improve the performance. To pinpoint the main cause of the degradation of circuit performance you have to neglect all, but a few parasitic devices. I stand for neglecting the unimportant parasitics, but of course it needs care.