Floor Plan Row Spacing

Is there any rule that determines row spacing in Cadence Encounter floor planning? I have done place and route with and without specifying the row spacing, and sometimes get routing violations. What is the rule of thumb?

Yes, the LEF file defines the row size. Row spacing should be zero unless you have a good reason for it.

Maybe you are talking about cell padding and got your concepts wrong?

Thanks Sam (can I call you that?). Yes, I do mean "row spacing". You find this setting when you go to specify floor plan > advanced settings. Thanks.

inputoutput said:

Thanks Sam (can I call you that?). Yes, I do mean "row spacing". You find this setting when you go to specify floor plan > advanced settings. Thanks.

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Use 0. This is a setting for really old technologies that had channels in between rows. I haven't seen that since 1um technology.

Less about the L than the number of metal levels, although
these have both moved forward. But since there is still cost
sensitivity and foundries do offer reduced stack height flows,
if you are (say) designing an IP block for all variants you
might find yourself constrained to use (say) only the bottom
three levels and then see it turn out that a semi-channel-style
is optimal.

I've used RF CMOS flows that the company said were for
"RF integration" (i.e. with digital) and had only 3 metal layers
total (one so thick / fat as to be useless for logic) at 0.5
and 0.25um. So you bet I used a channel style. But I did
the routing by hand, 20Kgates worth, after manually laying
out the first batch of the "standard cells" (one-off library,
bare-complementary-clocked FFs and so on, going for raw
speed and no care for density). Not autorouted. Channel
height compressed after all of the routes had been made,
by select-and-drag.

Not everybody gets to use 11 layers of fine pitch metal
and throw the bottom layer away (route-wise).