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using variables or signals in procedure

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mahmood.n

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Trying to use "procedure" in a vhdl code, I have been confused with using variables or signals. Consider the following code

Code: 
entity proc_adder is
	port( a,b: in bit_vector(1 downto 0);
	cin: in bit;
	sum: out bit_vector(1 downto 0);
	cout: out bit);
end;
architecture proc of proc_adder is
procedure full_adder( a, b, c: in bit; s, co: out bit) is
begin
	s := a xor b xor c;
	co := (a and b) or (a and c) or (b and c);
end;
begin
	process( a, b, cin )
	  variable carry: bit;
	begin				
		full_adder( a(0), b(0), cin, sum(0), carry);
		full_adder( a(1), b(1), carry, sum(1), carry);
	end process;
end;

It says: Formal "s" of class variable must be associated with a variable. If I use a variable in the process and then assign the variable to sum, then it will be OK. I wonder why I get that error. Does that mean, I have to pass only variables to a procedure? If the answer is yes, then why passing a(0) and .. as inputs don't have such problem.
 

In VHDL, the default class of a "in" on a procedure is constant, and the default class for an "out" is a variable. "Out" cannot be constant
In a procedure call, variables must be connected to variables, and signals must be connected to signals. Constants can be connected to anything.

Your code has the s an co as variables. Hence they must be connected to variables.
If you want to connect them to signals, then decalre them as signals:

Code VHDL - [expand]
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procedure full_adder( a, b, c: in bit; signal s, co: out bit) is
begin
    s := a xor b xor c;
    co := (a and b) or (a and c) or (b and c);
end;
 

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