robertocastiglioni
Newbie level 2
Hi, I'm a engineering student and I would like to know if anyone could help me to solve this exercise. From already thank you very much
Show synthesizable VHDL code for a register unit that performs
operations shown below. The unit has a 3-bit mode (md) input, an
asynchronous reset (rs) input, a 1-bit output control (oc) input, and an
8-bit bi-directional io bus. The internal register drives the io bus
when oc is ‘1’ and md is not “111”. Use std_logic.
md=000: does nothing
md=001: right shift the register
md=010: left shift the register
md=011: up count, binary
md=100: down count, binary
md=101: complement register contents
md=110: swap right and left 4 bits
md=111: parallel load
Show synthesizable VHDL code for a register unit that performs
operations shown below. The unit has a 3-bit mode (md) input, an
asynchronous reset (rs) input, a 1-bit output control (oc) input, and an
8-bit bi-directional io bus. The internal register drives the io bus
when oc is ‘1’ and md is not “111”. Use std_logic.
md=000: does nothing
md=001: right shift the register
md=010: left shift the register
md=011: up count, binary
md=100: down count, binary
md=101: complement register contents
md=110: swap right and left 4 bits
md=111: parallel load