LatticeSemiconductor
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This is my 1st time using Vivado Design Suite. I need a FIFO. Where can I get the component declarations of Xilinx for parametric module instantiation?
thanks
thanks
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This is my 1st time using Vivado Design Suite. I need a FIFO. Where can I get the component declarations of Xilinx for parametric module instantiation?
thanks
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 --! --! fifo component --! component pmi_fifo is generic ( pmi_data_width : integer := 18; -- (2 - 256) pmi_data_depth : integer := 256; -- pmi_full_flag : integer := 256; -- (1 - data_depth) pmi_empty_flag : integer := 0; -- pmi_almost_full_flag : integer := 252; -- (1 - 512) pmi_almost_empty_flag: integer := 4; -- (1 - 512) pmi_regmode : string := "reg"; -- "reg", "noreg" : enable registered output pmi_family : string := "EC" ; -- EC, ECP3, XO, XO2 module_type : string := "pmi_fifo"; -- pmi_implementation : string := "LUT" -- "EBR", "LUT" ); port ( Data : in std_logic_vector(pmi_data_width-1 downto 0); Clock : in std_logic; WrEn : in std_logic; RdEn : in std_logic; Reset : in std_logic; Q : out std_logic_vector(pmi_data_width-1 downto 0); Empty : out std_logic; Full : out std_logic; AlmostEmpty : out std_logic; AlmostFull : out std_logic ); end component pmi_fifo; --! --! instanciate EXAMPLE --! I0_EXAMPLE : pmi_fifo generic map ( pmi_data_width => 18, pmi_data_depth => 256, pmi_full_flag => 256, pmi_almost_full_flag => 252, pmi_almost_empty_flag => 4, pmi_regmode => "reg", -- "reg", "noreg" pmi_family => "ECP3" , pmi_implementation => "EBR" -- "EBR", "LUT" ) port map ( Data => svEXAMPLEData , Clock => sfEXAMPLECLK , WrEn => sfEXAMPLEWrEn , RdEn => sfEXAMPLERdEn , Reset => sfEXAMPLERST , Q => svEXAMPLEQ , Empty => sfEXAMPLEE , Full => sfEXAMPLEF , AlmostEmpty => sfEXAMPLEAE , AlmostFull => sfEXAMPLEAF ); signal svEXAMPLEData: std_logic_vector (18-1 downto 0); --! EXAMPLE input data signal sfEXAMPLECLK : std_logic; --! EXAMPLE Clock signal sfEXAMPLEWrEn: std_logic; --! EXAMPLE write enable signal sfEXAMPLERdEn: std_logic; --! EXAMPLE read enable signal sfEXAMPLERST : std_logic; --! EXAMPLE assynchronous reset, active high signal svEXAMPLEQ : std_logic_vector (18-1 downto 0); --! EXAMPLE output data signal sfEXAMPLEE : std_logic; --! EXAMPLE empty flag signal sfEXAMPLEF : std_logic; --! EXAMPLE full flag signal sfEXAMPLEAE : std_logic; --! EXAMPLE almost empty flag signal sfEXAMPLEAF : std_logic; --! EXAMPLE almost full flag
Are you looking for the unimacros library?
I'm not really getting why it is a problem to use the core generator tool to make a FIFO with the options you want or to run a tcl script that generates a FIFO core.
-> this also happens easily with invalid generics on your PMI.Then simulating/testing and realizing the depth was wrong