jinbow
Newbie level 3
Hi All,
Is it ok to have a Register made out of a Procedure (sub program) in VHDL?? Is it synthesizable??
EXAMPLE:
Can this be called directly inside the Architecture or does it have to be called inside a Process??
Will both cases be synthesized as an actual Register technology?? And can this be used universally for all vendors/tools??
I'm a bit confused since usually when a register is declared inside a Process(clk), a sensitivity list is used to execute the process whenever clk changes.
But if it is called under the Architecture without a Process, there won't be a sensitivity list.
Although in this code, it doesn't matter since it will only be executed under the rising_edge(clk).
Just want to get your thoughts, please advise.
Thanks,
ALbert
Is it ok to have a Register made out of a Procedure (sub program) in VHDL?? Is it synthesizable??
EXAMPLE:
Code:
[syntax=vhdl]
procedure REG
(signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic)
is begin
if rising_edge(clk) then
q <= d;
end if;
end procedure;
[/syntax]
Can this be called directly inside the Architecture or does it have to be called inside a Process??
Will both cases be synthesized as an actual Register technology?? And can this be used universally for all vendors/tools??
I'm a bit confused since usually when a register is declared inside a Process(clk), a sensitivity list is used to execute the process whenever clk changes.
But if it is called under the Architecture without a Process, there won't be a sensitivity list.
Although in this code, it doesn't matter since it will only be executed under the rising_edge(clk).
Just want to get your thoughts, please advise.
Thanks,
ALbert