Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Can't we use initial statement in interface block in system verilog?

Status
Not open for further replies.
U

u24c02

Advanced Member level 1
Joined
May 8, 2012
Messages
404
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,101
Hi.

When I use initial statement in interface block in systemverilog, it have some compile error.

Can't we use inital statement in interface block?
 

You can certainly use initial or always blocks inside an interface. Please provide the error.
 

The error message is following that ' a clocking output must be driven by a clocking drive'

Why is the error happening?
Code: 
clocking cb@ (posedge clk);
Output data, read , addr;
Read enable;
Endclocking

...

Module tb(...)
initial begin
...
tb.cb.read  = 1 ;
...
End

I found it.
It should be <= not =..the reason but I don't know.
 

Your error message had nothing to do with initial blocks.

See 14.16.1 Drives and nonblocking assignments in the 1800-2012 LRM for an explanation of the syntax.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top