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Help with arcane VHDL errors please in isplever

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Stuck using Lattice isplever (with VHDL-93?) fo ispmach 4064V
My full code is at https://pastebin.com/Dc4mCFVc but here's the problem area

Code VHDL - [expand]
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-- 70 The Above provides FM timing 
    --  Counting hbd(=pulse length)twice as fast as fm for 50% duty cycle.
    if (rising_edge (clock)) then
        if (hbd > 0) then
            hbd <= (hbd -1);
            dlyq <= '1';
        else    dlyq <= '0';    --This is the 5th occurrence of dlyq
        end if;
        if dlyq = lst then
            if (dlyq = '1') then hb <= "0101";
            else   hb <= "1010";
            end if;
-- 81 If dlyq is different to lst, it has changed state
        else hb <= "1100";
        --Turns off all hbridge transistors for one cycle
        end if;
        lst <= dlyq;
    end if;


If anyone can tell me what's wrong, or how to watch for a rising edge on an input, I'd love to know. It seems I can only watch rising edges on clocks. The warnings & error ispLever throws are:
Code VHDL - [expand]
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@W: CL117 :"C:\users\dec\projects\tranceiver\fmgen.vhd":58:1:58:2|Latch generated from process for signal dlyd(3 downto 0); possible missing assignment in an if or case statement.
@W: CL117 :"C:\users\dec\projects\tranceiver\fmgen.vhd":58:1:58:2|Latch generated from process for signal start; possible missing assignment in an if or case statement.
@W: CL179 :"C:\users\dec\projects\tranceiver\fmgen.vhd":73:1:73:2|Found combinational loop at hbd[0]
@W: FX105 :"C:\users\dec\projects\tranceiver\fmgen.vhd":74:6:74:12|Found combinational loop at hbd18
@W: CL179 :"C:\users\dec\projects\tranceiver\fmgen.vhd":73:1:73:2|Found combinational loop at hbd[1]
@W: CL179 :"C:\users\dec\projects\tranceiver\fmgen.vhd":73:1:73:2|Found combinational loop at hbd[2]
@W: CL179 :"C:\users\dec\projects\tranceiver\fmgen.vhd":73:1:73:2|Found combinational loop at hbd[3]
@W: FX105 :"C:\users\dec\projects\tranceiver\fmgen.vhd":73:1:73:2|Found combinational loop at dlyq
@E: CL123 :"C:\users\dec\projects\tranceiver\fmgen.vhd":73:1:73:2|Logic for dlyq_5 does not match a standard flip-flop


Don't take them too seriously - it's guessing :-(. I think it's line 73, but nothing I try there works.
 
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You google search phrase should be:
"common errors in vhdl code" or "VHDL coding tips and tricks"!
Read any one of them and your answer will be there!
 

Firstly it's a warning message, not an error. Do you understand the difference?

Secondly, you have been cutting the wrong code part. Assignments controlled by a clock edge sensitive condition never generate latches respectively combinational loops.

But there a lot of combinational loops in a different part of the code:
Code: 
57.-- 56 No rising edge check possible on halfclock, so needs half to avoid double pulsing.
58.    if (half = '0' and (halfclock = '1')) then  
59.        if (start = '0') then 
60.        hbd  <= cnt;
61.        dlyd <= cnt;
62.        start <= '1';
63.        end if;
64.-- 63 That lot provides a startup pulse.
65.    elsif ((dlyd = "0001" and data = '1') or ( dlyd = "0000")) then
66.            hbd <= (cnt - 1);
67.            dlyd <= cnt;
68.            dlyq <= '1';
69.    else    dlyd <= (dlyd -1);   
70.    end if;
71.

At first sight, at least the "combinational" counter will never synthesize to functional hardware:
Code: 
dlyd <= (dlyd -1);
 

A process shouldn't have both edge sensitive and level sensitive code in the same process. Your sensitivity list is filled with a bunch of signals some (like the clock) will trigger the process for the combinational logic portion of the code. You should separate combinational logic from the sequential clocked logic. This would also result in compilation errors with signals being driven from two processes, which is what you are really doing (how are you supposed to both generate combinational logic and sequential logic for the same signal at the same time?).
 

Thank you very much for your time and wisdom, gentlemen.

We did a vhdl module at University, but this makes me realize how lazy the guy actually was. Going for a substantial rewrite in line with criticism, as this code needs to be good, and timed well. That rewrite will be slow, as I am currently recovering from a stroke. But I'll get there.
 

I did a late degree of sorts and prototyped this in discrete hardware using 74AUC, with a 74AUC16374 (16 D flip-flops), so I have a hardware control strategy known to work that I can replicate.

My one remaining question is: How should I recreate in vhdl(for internal use only) an array of 16 or so flip flops with addressable Ds & Qs? A shift register?

I have hardware I can replicate in vhdl. The only refinement I added was switches for adjusting how many clock cycles for a high or low, to allow variation of speed over Plastic Optical Fibre. This is a prototype. I can deal with the switches, even though I realize my VHDL is badly polluted by C code for PICs :-/.
 

Not sure if I understand the question right, you can model any existing discrete logic in VHDL, or add features that are not provided by the respective logic chips. The design is only limited by the available amount of 64 macro cells. Asking how presumes a clear description of intended function which I don't see yet.
 

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