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[SOLVED] how to write a vhdl program with two conditional statements

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prashanthi999

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hello guys, im missing some pulses in my conditional statement, kindly guide me, here are my conditional statements, the conditions are not getting updated at the rising edge clock cycle.

Code: 
process (clk)
   begin
	   if( ce = '1') then
			if s = '0' and c = '0' then 
					 zr <= xr;
					 zr1 <= xr1;
					 zi <= xi;
					 zi1 <= xi1;
			elsif s = '0' and c = '1' then 
					 zr <= xr;
					 zr1 <= xi1;
					 zi <= xi;
					 zi1 <= xr1;
			elsif s = '1' and c = '0' then 
					 zr <= xr + xr1;
					 zi <= xi + xi1;
					 zr1 <= xr - xr1;
					 zi1 <= xi - xi1;
			else
					 zr <= xr + xi1;
					 zi <= xi - xr1;
					 zr1 <= xr - xi1;
					 zi1 <= xi + xr1;
			end if;
      end if;			
   end process;
end Behavioral;
 

To get an update at rising edge, both in simulation and synthesized hardware, you'll use a rising_edge(clk) condition.

Code: 
process (clk)
   begin
     if rising_edge(clk) then
       if ce = '1' then
          ....
       end if;
     end if;
   end process;
 
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