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Vhdl code for square ?

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napiuuul

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do the vhdl can use expression * as a multiplication? i want to square input x at vhdl
 

Code VHDL - [expand]
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library ieee;
use numeric_std.all;
 
entity square is
  port (
    x           : in  unsigned( 7 downto 0);
    x_squared   : out unsigned(15 downto 0)
  )
end entity square;
 
architecture rtl of square is
begin
  x_squared <= x*x;
end architecture rtl;
 

i want to create program that have expression -> (x divided ((y/100) squared))) {x and y = input}. this vhdl code will be implemented with FPGA-DE1 board. input consist binary number.. can you help me?
 

napiuuul said:
i want to create program that have expression -> (x divided ((y/100) squared))) {x and y = input}. this vhdl code will be implemented with FPGA-DE1 board. input consist binary number.. can you help me?
Click to expand...
Post the code that you've written so far, including your testbench...then ask for help. Asking for help before you've expended even minimal effort, or explained why you are unable to expend such minimal effort, is showing that you're lazy.

Kevin
 

whats wrong with the VHDL expression:

op <= x/ ( (y/100) **2 ) ;
 

whats wrong with the VHDL expression:
Click to expand...

A pretty good question. You can implement the code as written and it synthesizes to (basically) working hardware, as the RTL viewer shows

Code VHDL - [expand]
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entity test1 is
    port 
    (
        x   : in integer range 0 to 1023;
        y   : in integer range 0 to 1023;
        op  : out integer range 0 to 1023
    );
 
end entity;
 
architecture rtl of test1 is
begin
    op <= x/ ( (y/100) **2 ) ; 
end rtl;


rtl.png

Finding out what's possibly wrong with the solution would involve a considerable learning curve.
 

napiuuul said:
i want to create program that have expression -> (x divided ((y/100) squared))) {x and y = input}. this vhdl code will be implemented with FPGA-DE1 board. input consist binary number.. can you help me?
Click to expand...

First, divisions should be avoided where possible. The (y/100) isn't needed, and the expression can become (10000 * x / (y**2)).

The first real question is how much precision is needed by the division by non-power of two. In fixed-point, you can have integral and fractional bits. eg, 6.25 becomes 0110.0100 . From there you should size the inputs/outputs/intermediates to ensure no overflow and sufficient precision.

The second question is performance. At what rate do you need to process new inputs? How much delay can you allow for processing.

The last question is area vs engineering time. If bandwidth/latency isn't a large concern, is there any value in trying to make a smaller implementation? In some cases this is critical, in others it wastes a large amount of development time for very little benefits.
 

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