systemc in comparison to VHDl

Hello
Can anybody explain me systemC in comparison to VHDL?
Thanks

VHDL is an HDL (hardware description language).
System C is a modelling language.

share with me some more point please.

Like what?
They are two different languages.
If you want to put a design on an FPGA, then you need VHDL.

VHDL or Verilog are "Hardware Description Languages" - There're used for explicit and accurate synthesis of digital circuits with very little ambiguity.

System C on the other hand is used for high level system modeling.

Comparing between the 2 is like comparing between Matlab and Assembler...
This may help you understand:

https://www.doulos.com/knowhow/systemc/tutorial/modules_and_processes/

This seems like a very broad homework or interview question.

SystemC is a C++ library used to model hardware systems at many different levels of abstraction. A very restrictive subset of that library can be used to synthesize a description into real hardware. However, it's main purpose is to provide high-level, high-performance models of a system to get qualitative analysis of the system, and to interact with system firmware/software in advance of having the actual hardware to run on.

VHDL is a hardware description language that can also model hardware systems at many different levels of abstraction. However, it's main purpose is to model a description that can be synthesized into real hardware.

You will find each tool easy to describe, and get the best performance using the abstraction it is best at describing.