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Help for VHDL code, definition of matrix 2D

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Adnan86

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Hi
i defined matrix as :
Code: 
type matrix_2D is array (integer range <>, integer range <>) of signed(31 downto 0);
and because of multiplication i had to in 2 Dimension .
but i want to give initials to 2 signal as matrix , but ones just have 1 row and ones just have one column .
and i said i had to define them as 2 Dimension .
Code: 
signal a : matrix_2D(1 to 1,1 to 3 ) := (1;3;4);
signal b : matrix_2D(1 to 3,1 to 1 ) := (1,3,4);
but i have this error :
String literal foun where type sub_way #2 of matrix_2d , whose element type .... is not an enumeration type , was expected .
and now ehat can i do ? please help ? and please don't say change your type matrix as 1D , because i need to be 2D ,
thanks a lot
 

several problems here:

1. the numbers 1, 3 and 4 are not signed numbers. They are integers. You need to convert them to a signed type. to_signed(1, 32);
2. You never use ; inside an array literal. For an array, separations are done with a ,
3. You need to group your results:

Code: 
signal a : matrix_2D(1 to 1,1 to 3 ) := ( ( to_signed(1, 32), to_signed(3, 32), to_signed(4, 32) ) );
signal b : matrix_2d(1 to 3, 1 to 1) := ( ( to_signed(1, 32) ), ( to_signed(3, 32) ), ( to_signed(4, 32) ) ) );
 
TrickyDicky said:
several problems here:

1. the numbers 1, 3 and 4 are not signed numbers. They are integers. You need to convert them to a signed type. to_signed(1, 32);
2. You never use ; inside an array literal. For an array, separations are done with a ,
3. You need to group your results:

Code: 
signal a : matrix_2D(1 to 1,1 to 3 ) := ( ( to_signed(1, 32), to_signed(3, 32), to_signed(4, 32) ) );
signal b : matrix_2d(1 to 3, 1 to 1) := ( ( to_signed(1, 32) ), ( to_signed(3, 32) ), ( to_signed(4, 32) ) ) );
Click to expand...

about 1,2,3 it's just an example that i said , i knew used signed of them .
here my code :
Code: 
constant a_in : matrix_2D(1 to 1 ,1 to 19) := (
x"00000033", x"0000004b", x"0000004b", x"0000004b", x"ffffffd7",
x"ffffff6a", x"0000004b", x"0000004b", x"00000021", x"ffffff6d",
x"0000004b", x"0000004b", x"00000041", x"ffffff6a", x"ffffff6a",
x"ffffff6a", x"ffffffe6", x"0000004b", x"00000041");
and used 2 more (), as you said , i changed it as you said but didn't worked ...
 
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because the first dimension only has a length of one, its being a little picky.

try this:

Code: 
constant a_in : matrix_2D(1 to 1 ,1 to 19) := ( 1 => (
x"00000033", x"0000004b", x"0000004b", x"0000004b", x"ffffffd7",
x"ffffff6a", x"0000004b", x"0000004b", x"00000021", x"ffffff6d",
x"0000004b", x"0000004b", x"00000041", x"ffffff6a", x"ffffff6a",
x"ffffff6a", x"ffffffe6", x"0000004b", x"00000041" ) );

I am a bit concerned though - what do you think this array will acheive? why 32 bits, most hardware multipliers are 18 bit natively.
 
TrickyDicky said:
because the first dimension only has a length of one, its being a little picky.

try this:

Code: 
constant a_in : matrix_2D(1 to 1 ,1 to 19) := ( 1 => (
x"00000033", x"0000004b", x"0000004b", x"0000004b", x"ffffffd7",
x"ffffff6a", x"0000004b", x"0000004b", x"00000021", x"ffffff6d",
x"0000004b", x"0000004b", x"00000041", x"ffffff6a", x"ffffff6a",
x"ffffff6a", x"ffffffe6", x"0000004b", x"00000041" ) );

I am a bit concerned though - what do you think this array will acheive? why 32 bits, most hardware multipliers are 18 bit natively.
Click to expand...

Thank you for help , it's worked . it means i defined a_in in package and when i compiled it now give me no error but when i call him in i have this error :
constant "a_in" is type sub-array #1 of work.package.matrix_2d ; expecting type sub-array #1 of work.package.matrix_2d .

when i want to call it , i just used : a_in and not use index because i call whole of a_in, so if
how i should call it , if i don't want to use : a_in(1,1) or a_in(1,2) or .... just call whole a_in .
about use of 32 bit , i didn't know that for multiplication we can't use more 18 bit , you mean for simulation with xilinx and virtex4 , i can't use 32 bit for multiplication ?
thanks for help
 
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Its difficult to understand what you're saying without a code example. It is always best to copy/paste the code AND the actual errors.

Multipliers on the FPGA are 18x18 (giving 36 bit result). A 32 bit multiply requires 4 18x18 multipliers.
You need to understand the base hardware before writing VHDL.
 
yes you right , without code it's hard to understand , but whole code it's too long and have several package , but main part of my code it's :
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 

package matrix_pkg is

type matrix_D2 is array (integer range <>, integer range <>) of signed(31 downto 0);

constant a_in: matrix_D2(1 to 1,1 to 19) := (1=>(
x"00000033", x"0000004b", x"0000004b", x"0000004b", x"ffffffd7",
x"ffffff6a", x"0000004b", x"0000004b", x"00000021", x"ffffff6d",
x"0000004b", x"0000004b", x"00000041", x"ffffff6a", x"ffffff6a",
x"ffffff6a", x"ffffffe6", x"0000004b", x"00000041" ));
end ;
------------------------------------------------------------
LIBRARY IEEE;
USE work.matrix_pkg.all ;

USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY test01 IS
   GENERIC (F : integer:=8;
            E : integer:=1);
   PORT (
      featurs_in: IN matrix_D2(1 to F, 1 to E); -- 8x1 matrix ;
      ready_class : out std_logic := '0' ;
      class_out: OUT  std_logic_vector(1 downto 0)
   ) ;
END test01;
ARCHITECTURE rtl OF test01 IS
COMPONENT test02 IS    
   GENERIC (M : integer:=3;
            N : integer:=2;
            K : integer:=1;
            L : integer:=1);
   
   PORT (
      a_in: IN matrix_D2(1 to M, 1 to N); -- MxN matrix ; -- 19x8
      b_in: IN matrix_D2(1 to N, 1 to K); -- NxK matrix ; -- 8x1
      c_in: IN matrix_D2(1 to L, 1 to M); -- LxM matrix ; -- 1x19
      clk: IN STD_LOGIC;
      reset: IN STD_LOGIC;
      ready : out std_logic := '1' ;
      d_out: OUT  matrix_D2(1 to L, 1 to K)-- LxK matrix ;
   ) ;
   END COMPONENT;
component ... is
.
.
end component ;
component ... is
.
.
end component ;
component ... is
.
.
end component ;

SIGNAL ready_1,ready_2,ready_3 : std_logic ;
SIGNAL out_1,out_2,out_3 :  matrix_D2(1 to 1, 1 to 1);
..
..
..
test02_1 : test02 
         generic map (19,8,1,1)  
         port map  (bbb_in, featurs_in, a_in, clk, reset, ready_1, out_1); 
-- bbb_in it's also like a_in , it's matrix but it's too long to used it in herem;
..
..
..
..
..
end  rtl ;

- - - Updated - - -

i have this error :
constant "a_in" is type sub-array #1 of work.matrix_pkg.matrix_d2 ; expecting type sub-array #1 of work.matrix_pkg.matrix_d2 .
i change some names for easy understanding ; i have no syntex error ,

about use 18x18 bit in vhdl , you right i should learn base of vhdl , after that learn it , but we should start it with example or project or any thing else to learn more,
 
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From the code you posted, you have missmatching sizes - thats the error.
 
TrickyDicky said:
From the code you posted, you have missmatching sizes - thats the error.
Click to expand...
no no no missmatching size , if you talk abou generic port for component :
Code: 
GENERIC (M : integer:=3;
            N : integer:=2;
            K : integer:=1;
            L : integer:=1);
i changed them in generic map :
Code: 
 generic map (19,8,1,1)
so i didn't think so ;
 
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Please post the whole code, and the exact errors.

Your whole setup is very complicated, and almost definately will not work in an FPGA. So the whole lot will probably need to be re-written
 
TrickyDicky said:
Please post the whole code, and the exact errors.

Your whole setup is very complicated, and almost definately will not work in an FPGA. So the whole lot will probably need to be re-written
Click to expand...
Thanks i solved my problem ;
 
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