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Is while loop in vhdl synthesizable

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emmagood

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Hello,

is while loop in VHDL synthesizable. I was trying to implement a code and got the following error:

ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more.
Click to expand...

It is a basic code:

Code VHDL - [expand]
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**************************
process(binary)
variable i : integer := 0;
begin
gray(3) <= binary(3);
while i < 3 loop
gray(i) <= binary(i) xor binary(i-1);
i := i+1;
end loop;
end process;
*************************


I also tried by using the xilinx solution to increase the no. of iterations (but was unable to do so) for 8.1 i. As this is just a basic code, I am guessing that no. of iterations may not matter.

Pls advise.

Thanks,
Emma Good
 
Last edited by a moderator:

Initialize variable i inside begin statement.Then it wont give Non-static loop limit exceeded error and also the fallowing statement gives a index out of range error when i is 0.
gray(i) <= binary(i) xor binary(i-1);
 
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Some VHDL tools accept a while loop with constant iteration range, others don't. Either ISE expects an explicite i:=0 before the loop or it doesn't support while loops at all. But instead of guessing about it, why don't you use a for loop, which is supported by any synthesis tool?
 

Hi,
That code seems to be combinational logic.to be sure if it is synthesizable just open your while loop and see is any physical constraint violated or not(i.e. multiple source,bad index, etc).
Regards
 

As kommu4946 pointed out, the variable initialialization is in the wrong place. The process will execute every time "binary" changes, and "i" will only start a 0 in the first execution.
"i" will increment forever, the Gray coding will only be done in the first call, and the code is not synthesizeable.

I agree with other posters that it is much better to use a "for" loop.

I think it is time for you to start using a simulator and a test bench. To do design by synthesizing and then debug in the lab is a great way to waste a lot of time.
A complex project will never be completed without a simulator.
 
OK point accepted. Which free simulator do you advise. I have the free version of Xilinx ISE (latest). Also be kind enough to point me to any book/ site which has a collection of projects to start of with (in case I am unable to make the project, I will have a ready solution in hand). I was using 'while' loop just to see its usage.

Other than that, I apologize for the late response.



Emma.
 
Last edited:

ISE 14.7 has a simulator included called ISIM, you could try starting with that.
 

I am looking for VHDL based resources pls. Also any compilation of projects will be highly appreciated.
Thanks.
 

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