neocool
Member level 4
Greetings everyone,
I had a question regarding testing signals in VHDL program. Using the ports tied to signals creates a big overhead when using many modules within the design since you have to interface them as well.
I've heard that the signals described in the package are visible in the simulation test bench and you can quickly add/remove them in one place (the package itself) whenever you need to test something.
The following did not work for me. The signal from the package did not appear on Webpack ISE and Modelsim.
PACKAGE:
INSIDE THE MODULE:
Why does not it work?
Thanks for the help in advance
I had a question regarding testing signals in VHDL program. Using the ports tied to signals creates a big overhead when using many modules within the design since you have to interface them as well.
I've heard that the signals described in the package are visible in the simulation test bench and you can quickly add/remove them in one place (the package itself) whenever you need to test something.
The following did not work for me. The signal from the package did not appear on Webpack ISE and Modelsim.
PACKAGE:
Code:
package monitor_signals is
signal monitor : bit;
end monitor_signals;
Code:
use work.monitor_signals.all;
-- make the "monitor"
-- signal visible
entity test is
port (...); --note: no need to define extra signal
end test;
architecture behave of test is
signal local : bit; -- a locally declared signal
-- which shall be monitored
begin
...
monitor <= local; -- copy the signal value to the
-- monitor signal
end behave;Why does not it work?
Thanks for the help in advance