Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] What's the utility of ..perl and Tcl /tk in Modelsim /Active Hdl ....Similar tools ?

Status
Not open for further replies.
blooz

blooz

Advanced Member level 2
Joined
Dec 29, 2010
Messages
560
Helped
121
Reputation
242
Reaction score
116
Trophy points
1,343
Location
India
Activity points
4,985
What's the Advantage of using these Scripting languages like perl tcl etc ...
How can we make benefit from them .....What's their role in verification stage ?
 

Is is very helpfull when you want to import/export an entire testbench with a .do file. You only have to call the .tcl in your .do file. You don't need to call manually the .tcl in your new project.

So if you only want to make 1 project its doesn't matter but if you want to make your project easy to export add everything into you .do file.
 

People use Tcl, Perl, or other scripting languages in verification for two distinct purposes.
  1. To control the execution of many different tests using essentially the same testbench. This is called Run Management. Maybe you have 100 tests and the only difference is which ROM file gets loaded. Each test will also have a separate log file, as well as other databases representing what was tested and what passed or failed. You want a summery of which test passed or failed, and want an easy way to see if the failures among the different tests are common or unique. Modeslsim/Questa has some tools that you can use in place of building your own scripts.
  2. To generate stimulus and check results. The Verilog language is mainly used for RTL design and does not have the software features needed to perform complex verification tasks. So people have turned to alternative scripting language to facilitate writing testbenches. SystemVerilog was designed to fill the gap between RTL and verification requirements by create a common language to be used by both.
 

Now i concentrate on Another Design Specialization ,however scripting languages have made many of those tasks simpler and easy to maintain often increasing productivity. I often use 0Python for my scripting ,it is simple and elegant.reducing human effort and increasing productivity that's what they mean in a nutshell ,Whether it is Tcl or Python.I have been using these scripting languages for many tasks like string manipulation.Interfacing with Web/Mail etc,resource management ,sometimes for Multicore Programming (especially the python Multiprocessing module.).I Personally prefer Python and I Like Perl and tcl too .I use Tcl for my digital design ..
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top