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breakdown voltage limitation on bulk to source(or Drain) for lower technologies

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Hi All


when we use core low voltage MOS(1v Device) working at higher voltage supply(1.8V) then i need to bias MOS such that voltage difference between Drain , Source & Gate are in safe limit(1v),
Do i also need 2 care for Bulk to Source(or Drain) voltage protection ?
As Bulk to Source(or Drain) junction is always reverse bias, then what will happen when Vbd is put at 1.8V for 1V device ?

Thanks
Gaurav
 
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Yes, u need to consider the breakdown between source and bulk. The exact breakdown voltage depends on your process. Pls consult with your process contact window.
 

Thanks Leo, But i want to understand which effect results in Bulk-source(or drain) breakdown, Like gate-source(or drain) breakdown occurs due to hotelectron effect, gate leakage etc.
Bulk-Source/Drain Breakdown can only occur due to avalanche effect of reverse bias junction, but it will happen at much higher voltage than gate breakdown at lower technologies, m i right or wrong ?
 

Below 0.5um your Vbs is likely not the limiting voltage anymore.
Only a very shallow well that sees punchthrough / reach-through
would break at less than 5V. The oxide and short channel Vds
punchthrough will be much lower. But perating at high Vbs
position gives you a bad gate voltage adder via body effect
and if you respect Vgs potential you may violate Vgb (which
is the same limit-wise but not always spec'd separately).
 
Yes. The breakdown is caused mainly by the junction. However, you still need to check the space between the source contact and the bulk contact. Some process allows zero space like butting. So it depends on the process design rule and layout.
Someone had experienced this kind of failure.
ravi_free said:
Thanks Leo, But i want to understand which effect results in Bulk-source(or drain) breakdown, Like gate-source(or drain) breakdown occurs due to hotelectron effect, gate leakage etc.
Bulk-Source/Drain Breakdown can only occur due to avalanche effect of reverse bias junction, but it will happen at much higher voltage than gate breakdown at lower technologies, m i right or wrong ?
Click to expand...
 

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