# designing a 4 bit counter

1. ## designing a 4 bit counter

how do i design a 4 bit counter using d flip flops
thanks

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2. ## Re: designing a 4 bit counter

I assume you want a synchronous counter - Use the D flip flop excitation table and draw up your circuit excitation table with your present and next states. Use Karnaugh maps to solve for your D value for each flip flop(4 in your case 'coz it's a 4-bit counter).
Here's a solution actually:
http://www.csci.csusb.edu/schubert/t...f03/dw4bit.pdf

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3. ## Re: designing a 4 bit counter

Thanks alot

But what if I am constrained with 4 flipflops and only 3 logic gates
Do you have any idea how this will work??
Will it contain some sort of special feature ?

Thanks alot again

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4. ## Re: designing a 4 bit counter

What exactly are your design needs? The reason I ask is you can design a 4-bit asynchronous counter with just four D flip flops. If you have a requirement that states - count from (0000)b to (1100)b and not (1111)b, then you use NAND gates to asynchronously clear inputs of all flip flops once your counter reaches (1100)b. You could make a case for a similar asynch design which would use 4 FFs and 3 logic gates.

5. ## Re: designing a 4 bit counter

my only constraint is that the counter consists of 4 d flip flops and any 3 logic gates
I will try to implement it to count to 1100 as you told me
I hope it works
Thanks alot

I am really sorry

but can a counter count only even numbers??

I am really sorry for the disturbance but I can't figure it out

Thanks

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6. ## Re: designing a 4 bit counter

Yup, you can design a synchronous four bit even counter. Draw up your state table with your present and next states, use the D-flip flop excitation table and karnaugh maps and extract your D value for each of the flip flops and you have your even counter! I am not sure how many logic gates it will use though, maybe you can reduce it down to three gates...

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