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Help me out with a VHDL code issue

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mrdotcom1

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Dear All,
I have got my own VHDL code and inside that when i am writting bd_a:=bd_b1(10); then its ok where bd_a value is 0.0 at this place and its a real variable. But if I write bd_a:=bd_a+bd_b1(10); where as bd_a is still 0.0 it gives me error on synthesis that real operands can not be in this context.
Kindly suggest me regarding this.

Thanks and regards

Amit
 

Re: help required

i didn't review your code but real values are not synthesizable.
 

Re: help required

Dear Sir,

Thanks for your reply. But 1st kindly go through the code and then let me know. because while I omit only two lines from this code the rest of the code can be synthesised and even with all other real values. And even I do have few more earlier code where I have already synthesised real values.

But anyways my requirement is to convert real(floating numbers) to binary and binary to real(floating numbers) as well.

So help me out of these please by some means..

Thanks and regards
 

Re: help required

Refer to Xilinx synthesis guide present in %\Xilinx\doc\usenglish\books\docs\xst\ look out for real type..It has given many times in this doc that real type is not supported.Because it does not have any physical correspondence
i just had a glimpse of your code ....(Not reviewed yet) I think the codes having real values you think was synthesized successfully was the cases in which the real values were used for calculation purpose only.
If you want to use the real values you should use some standard notation with fixed precision for the same.

regards..
 

Re: help required

Real numbers are not synthesisable .if it is very much neseccary to use real number you can go for ipcores
 

Re: help required

Dear Nandini thanks for the suggession. I am working on that now...
 

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