Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Initialise asynchronous SRAM

Status
Not open for further replies.
G

grubby23

Junior Member level 3
Joined
Nov 22, 2007
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,606
vhdl ram data initialization rom

Hi

Until now i always used BRAM for memory. This could be easily initialise with values.
But now I have the problem that I need an asynchronous memory to read data out.

Anyone an idea how I can initialise this kind of ram? I am using XST 7.3 for synthesis.
Thanks for helpful comments
 

fpga initialize ram

Hello,

If it is a SRAM, in the beginning you have to initialise by writing zeros in all locations by using the proper control signals like WEN, CE and addresses.

If u need more info don't hesitate to ask me.

Thank you,
N.Muralidhara
 

distributed ram xst too long

muralicrl said:
Hello,

If it is a SRAM, in the beginning you have to initialise by writing zeros in all locations by using the proper control signals like WEN, CE and addresses.

If u need more info don't hesitate to ask me.

Thank you,
N.Muralidhara
Click to expand...

Hm, no i n some way I want to do as the same as with BRAM. THere I can specify in my VHDL file which contents to be stored in the RAM. So I wanna know if there is also a possiblity to define distributed RAM which is 1536 x 32 bit to hold values at start up, the ones that I specify in my VHDL file?

Many thanks!
 

initialization ram vhdl

You can create a large asynchronous RAM by using distributed RAM. Refer to section "RAMs and ROMs HDL Coding Techniques" in your XST User Guide, and search for the word "distributed" or "asynchronous".

You can also use Core Generator to create distributed RAM. Browse the "Basic Elements - Memory Elements" section. I don't recall which core is the best choice.

However, a large distributed RAM consumes a lot of logic fabric, and it takes a while to synthesize, and it will perform rather slowly. If possible, try to modify your project so it can use the much nicer synchronous BRAMs.

You don't have to add logic to your FPGA design just to initialize the RAM with zeros or some constant data. The FPGA configuration process can initialize the RAM for you. There are various way of specifying your desired initialization data, such as by using HDL initial statements or attributes, or core generator initialization files. Some of these methods are shown in the"RAMs and ROMs HDL Coding Techniques" section.
 

initializing ram vhdl

echo47 said:
You don't have to add logic to your FPGA design just to initialize the RAM with zeros or some constant data. The FPGA configuration process can initialize the RAMs for you. There are various way of specifying your desired initialization data, such as HDL initial statements or attributes, or core generator initialization files.
Click to expand...

Thanks for the feedback echo47, I am just using the Coregenerator to create me distributed RAM. There you can specify a .coe file with the initial values. So trying to get this first run in the simulation but still not sure what I have to do to get then this running on the FPGA. Do I have to specify the initial values for the distributed RAM in a constraint file? I have read this possibility with the INIT attributes but not sure how to apply this. Rewriting the code for synchronous memory is not really a solution, so I have to life for now with the long sythesis time and large logic!
 

xst initialise rom

It's been a while since I used coregen with a .coe file, but I think your .coe file should be sufficient for both simulation and synthesis, assuming all your tools are installed correctly. You shouldn't have to put your initialization data anywhere else.

The various INIT attributes can initialize data in an instantiated library primitive such as RAMB16_S18_S18, but the library doesn't provide any big distributed RAMs, so INIT probably won't be useful to you.

Also see "Initializing RAM Directly in HDL Code" in you XST User Guide. It shows how to create initialized RAM with a VHDL array, without using core generator or .coe file. That particular example looks synchronous, but the initialization technique should work with asynchronous distributed RAM too.
 

initialization ram vhdl

echo47 said:
Also see "Initializing RAM Directly in HDL Code" in you XST User Guide. It shows how to create initialized RAM with a VHDL array, without using core generator or .coe file. That particular example looks synchronous, but the initialization technique should work with asynchronous distributed RAM too.
Click to expand...

Well thats is exactly the problem, with the BRAM I can use this easy Initializing procedure, but unfortuantely this doesnt work with the distributed/asynchronous RAM.

Hope it works out with the coe file!

cheers
 

ramb16_s18_s18

Oh wait, you're using ISE 7.3i. I couldn't use version 7 because of bugs. The HDL memory initialization may be unsupported or not working properly. Can you upgrade to a modern version? I've seen great improvements in version 8 and 9.

I don't speak VHDL. This Verilog 64x16 asynchronous distributed ROM synthesizes fine in ISE 9.2.04i. Larger ROMs work too, the code simply gets longer:
Code: 
module top (addr, data);
  input   [5:0] addr;
  reg    [15:0] rom [0:63];
  output [15:0] data;

  initial begin
    rom[ 0]=64313; rom[ 1]=45804; rom[ 2]=16813; rom[ 3]=31955;
    rom[ 4]=55950; rom[ 5]=38894; rom[ 6]=12950; rom[ 7]= 8497;
    rom[ 8]=13144; rom[ 9]=41124; rom[10]=16391; rom[11]=54947;
    rom[12]= 4544; rom[13]=51590; rom[14]=29238; rom[15]=63755;
    rom[16]=17495; rom[17]=49541; rom[18]=43365; rom[19]=18498;
    rom[20]=27931; rom[21]=26724; rom[22]=50540; rom[23]=59099;
    rom[24]=63746; rom[25]= 6375; rom[26]=16127; rom[27]=63003;
    rom[28]= 5513; rom[29]=53091; rom[30]=22325; rom[31]=32963;
    rom[32]=59740; rom[33]=56116; rom[34]=56953; rom[35]=37646;
    rom[36]= 7179; rom[37]=43120; rom[38]= 5928; rom[39]=47343;
    rom[40]=65150; rom[41]=62776; rom[42]= 9213; rom[43]=64208;
    rom[44]=53917; rom[45]=14185; rom[46]=59718; rom[47]=51542;
    rom[48]=63828; rom[49]=51044; rom[50]=34328; rom[51]=12753;
    rom[52]=46895; rom[53]=61784; rom[54]=39033; rom[55]=53040;
    rom[56]=53926; rom[57]=  794; rom[58]=47707; rom[59]=27823;
    rom[60]= 9949; rom[61]=   74; rom[62]=  561; rom[63]=54549;
  end

  assign data = rom[addr];
endmodule
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top