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NEED HELP: Optimized blocks in VHDL design

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Hi there,

Can anyone help with some information about the optimization of the design within the Xilinx ISE 4.2i package? My problem is that the VHDL code that is written compiles perfectly, and the 'Simulate Behavioral VHDL Model' simulates pefectly, but when I run the design implementation stage, the design is optimized, and all the VCC and GND connections are removed (listed in the map report). If I run the 'Simulate Post-Translate VHDL Model' the simulation results are all X (red lines). Can anyone tell me why this happens?

Thanks,
Andrew
 

Occurrence of a uncertain condition 'X' is not connected in any way with removal nets GND and VCC. It is result not performance of time restrictions.Use TimingAnalyzer for the analysis of the project.
Set rigid restrictions on time for nets in which delay distributions of a signal are exceeded with the value necessary to you. Avoid several clocks in the project.
 

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