n_sanjay_n
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Hi,
I have written a comparator using bit slicing in VHDL. The code basically takes 2 vector inputs A and B, compares them and gives output C=A if A>B or else C=B. To do this, I first wrote a 1 bit comparator :
I want to use this in a generic width comparator and I wrote a code for the same. There are no errors in the code but the output is not as expected. In the program code below, I have instantiated the previous program and used the generate keyword to replicate it n times.
Here is the test bench (just in case):
I have written a comparator using bit slicing in VHDL. The code basically takes 2 vector inputs A and B, compares them and gives output C=A if A>B or else C=B. To do this, I first wrote a 1 bit comparator :
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 entity bit_slice is port ( A, B, Eq_in, Gt_in : in std_logic; Eq_op : out std_logic; Gt_op : out std_logic); end bit_slice; architecture arch_bit_slice of bit_slice is begin process (A, B, Eq_in, Gt_in) begin Eq_op <= (A xnor B) and Eq_in; if(Gt_in = '1') then Gt_op <= '1'; else Gt_op <= (Eq_in) and (A and (not(B))); end if; end process; end arch_bit_slice;
I want to use this in a generic width comparator and I wrote a code for the same. There are no errors in the code but the output is not as expected. In the program code below, I have instantiated the previous program and used the generate keyword to replicate it n times.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 entity prob is generic ( n : integer := 3); port ( A, B : in std_logic_vector((n-1) downto 0); C : out std_logic_vector((n-1) downto 0) ); end prob; architecture arch_prob of prob is component bit_slice port ( A, B, Eq_in, Gt_in : in std_logic; Eq_op : out std_logic; Gt_op : out std_logic); end component; signal t_Eq_in : std_logic_vector ((n) downto 0); signal t_Gt_in : std_logic_vector ((n) downto 0); signal t_Eq_op : std_logic_vector ((n) downto 0); signal t_Gt_op : std_logic_vector ((n) downto 0); signal temp : std_logic; begin prob2_gen : for i in (n-1) to 1 generate begin t_Eq_in(t_Eq_in'high) <= '1'; t_Gt_in(t_Gt_in'high) <= '0'; Ai: bit_slice port map ( A => A(i), B => B(i), Eq_in => t_Eq_in(i), Gt_in => t_Gt_in(i), Eq_op => t_Eq_op(i-1), Gt_op => t_Gt_op(i-1)); end generate prob_gen; temp <= t_Gt_op(t_Gt_op'low); process(temp) begin if(temp = '1') then C <= A; else C <= B; end if; end process; end architecture;
Here is the test bench (just in case):
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 library ieee; use ieee.std_logic_1164.all; entity tb_bit_slice is end tb_bit_slice; architecture arch_tb of tb_bit_slice is component prob generic ( n : integer); port ( A, B : in std_logic_vector((n-1) downto 0); C : out std_logic_vector((n-1) downto 0) ); end component; constant n_tb : integer := 3; signal t_A, t_B, t_C: std_logic_vector((n_tb-1) downto 0); begin U1 : prob generic map (n_tb) port map ( t_A, t_B, t_C); test_process : process begin t_A <= "100"; t_B <= "000"; wait for 100 ns; t_A <= "001"; t_B <= "010"; wait for 100 ns; t_A <= "110"; t_B <= "001"; wait for 100 ns; t_A <= "000"; t_B <= "110"; wait for 100 ns; t_A <= "101"; t_B <= "100"; wait for 100 ns; t_A <= "111"; t_B <= "111"; wait for 100 ns; wait; end process; end arch_tb;
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